CP3SP33SMSSLASHNOPB datasheet(300/407 Pages) TI1

300 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

3. If the ACBnCTL1.STASTRE bit is set, and the transaction was successfully completed (i.e., both the

ACBnST.BER and ACBnST.NEGACK bits are cleared), the ACBnST.STASTR bit is set. In this case,

the ACB stalls any further ACCESS.bus operations (i.e., holds SCLn low). If the ACBnCTL1.INTE bit is

set, an interrupt is asserted.

4. If the requested direction is transmit, and the start transaction was completed successfully (i.e., neither

the ACBnST.NEGACK nor ACBnST.BER bit is set, and no other master has accessed the device), the

ACBnST.SDAST bit is set to indicate that the module is waiting for service.

5. If the requested direction is receive, the start transaction was completed successfully, and the

ACBnCTL1.STASTRE bit is clear, the module starts receiving the first byte automatically.

6. Check that both the ACBnST.BER and ACBnST.NEGACK bits are clear. If either the

ACBnCTL1.INTEN or ACBnCTL1.DMAEN bit is set, an interrupt is asserted when either the

ACBnST.BER or ACBnST.NEGACK bit is set.

29.2.1.2 Master Transmit

After becoming the bus master, the device can start transmitting data on the ACCESS.bus. To transmit a

byte using interrupts or polling, software must:

1. Check that the BER and NEGACK bits in the ACBnST register are clear and the ACBnST.SDAST bit is

set. Also, if the ACBnCTL1.STASTRE bit is set, check that the ACBnST.STASTR bit is clear.

2. Write the data byte to be transmitted to the ACBnSDA register.

To transmit a byte using DMA, software must:

1. If the ACBnCTL1.DMAEN bit was set before the start transaction, a DMA request is generated

automatically at the end of the address transaction and each following transaction unless for some

reason (e.g., ACBCST, MATCH, or BER were set) an interrupt was asserted

2. When the ACBnST.NEGACK or ACBnST.BER bits are set, an interrupt is asserted, and the module

stops sending DMA requests.

When the slave responds with a negative acknowledge, the ACBnST.NEGACK bit is set and the

ACBnST.SDAST bit re- mains clear. In this case, if the ACBnCTL1.INTEN or ACBnCTL1.DMAEN bit is

set, an interrupt is asserted.

29.2.1.3 Master Receive

After becoming the bus master, the device can start receiving data on the ACCESS.bus. To receive a byte

using interrupts or polling, software must:

1. Check that the ACBnST.SDAST bit is set and the ACBnST.BER bit is clear. Also, if the

ACBnCTL1.STASTRE bit is set, check that the ACBnST.STASTR bit is clear.

2. Set the ACBnCTL1.ACK bit, if the next byte is the last byte that should be read. This causes a

negative acknowledge to be sent.

3. Read the data byte from the ACBnSDA register.

To receive a byte using DMA, software must:

1. The DMA request becomes active after the module receives a byte of data. If an error occurs during

the transaction (e.g., ACBCST.NMATCH or ACBST.BER is set), an interrupt is asserted and the DMA

operation is stalled.

2. Before receiving the last byte of data, set the ACBnCTL1.ACK bit. This should be done by

programming the DMA to interrupt the CPU one byte before the end of the transmission and letting the

software set the ACBnCTL1.ACK bit.

300

Dual ACCESS.bus Interfaces

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB Datasheet(PDF) 300 Page - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 300 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL