CP3SP33SMSSLASHNOPB datasheet(301/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

29.2.1.4 Master Stop

A Stop Condition may be issued only when this device is the active bus master (ACBnST.MASTRER = 1).

To end a transaction, set the ACBnCTL1.STOP bit before clearing the current stall bit (i.e., the

ACBnST.SDAST, ACBnST.NEGACK, or ACBnST.STASTR bit). This causes the module to send a Stop

Condition immediately, and clear the ACBnCTL1.STOP bit.

29.2.1.5 Master Bus Stall

The ACB module can stall the ACCESS.bus between trans- fers while waiting for the APB bus master

(CPU, DSP, or DMA controller) response. The ACCESS.bus is stalled by holding the SCLn signal low

after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus operation.

Software must make sure that the next operation is prepared before the bit that causes the bus stall is

cleared.

The bits that can cause a stall in master mode are:

•

Negative acknowledge after sending a byte (ACBnST.NEGACK = 1).

•

ACBnST.SDAST bit is set.

•

If the ACBnCTL1.STASTRE bit is set, after a successful start (ACBnST.STASTR = 1).

29.2.1.6 Repeated Start

A repeated start is performed when this device is already the bus master (ACBnST.MASTER = 1). In this

case, the ACCESS.bus is stalled and the ACB waits for software intervention to handle the condition:

negative acknowledge (ACBnST.NEGACK = 1), empty buffer (ACBnST.SDAST = 1), or a stop-after-start

(ACBnST.STASTR = 1).

For a repeated start:

1. Set the ACBnCTL1.START bit.

2. In master receive mode, read the last data item from the ACBnSDA register.

3. Follow the address send sequence, as described in “Sending the Address Byte” on page 225

4. If the ACB was waiting for handling due to ACBnST.STASTR = 1, clear it only after writing the

requested address and direction to the ACBnSDA register.

29.2.1.7 Master Error Detections

The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer or

the acknowledge cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal action is detected,

the BER bit is set, and the MASTER mode is exited (the MASTER bit is cleared).

29.2.1.8 Bus Idle Error Recovery

When a request to become the active bus master or a restart operation fails, the ACBnST.BER bit is set to

indicate the error. In some cases, both this device and the other device may identify the failure and leave

the bus idle. In this case, the start sequence may not be completed and the ACCESS.bus may remain

deadlocked.

To recover from deadlock, use the following sequence:

1. Clear the ACBnST.BER and ACBnCST.BB bits.

2. Wait for a timeout period to check that there is no other active master on the bus (i.e., the

ACBnCST.BB bit remains clear).

3. Disable, and re-enable the ACB to put it in the non-ad- dressed slave mode.

4. At this point, some of the slaves may not identify the bus error. To recover, the ACB becomes the bus

master by issuing a Start Condition and sends an address field. Then, it issues a Stop Condition to

synchronize all the slaves.

Dual ACCESS.bus Interfaces

301

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