CP3SP33SMSSLASHNOPB datasheet(295/407 Pages) TI1

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Shift Register

(High Byte)

Data

Write

Data

Out

MOD

MWnDAT

Shift Register

(Low Byte)

Read Buffer

(High Byte)

Read Buffer

(Low Byte)

Read

DS442

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

28.7.4 Microwire Module n Data Register (MWnDAT)

The MWnDAT registers are 16-bit, read/write registers used to transmit and receive data through the

MDODIn and MDIDOn pins.

MWDAT

Figure 28-8 shows the hardware structure of the register.

Figure 28-8. MWnDAT Register

29 Dual ACCESS.bus Interfaces

The ACCESS.bus interface modules (ACB) provide a two- wire serial interface compatible with the

ACCESS.bus physical layer. It permits easy interfacing to a wide range of low-cost memories and I/O

devices, including: EEPROMs, RAMs, timers, A/D converters, D/A converters, clock chips, and peripheral

drivers. It is compatible with Intel’s SMBus and Philips’ I2C bus. The ACB modules can be configured as a

bus master or slave, and can maintain bidirectional communications with both multiple master and slave

devices

Two modules are provided, module 0 on the CPU APB bus and module 1 on the shared audio peripheral

APB bus. Module 1 can be accessed by either the CPU or DSP, so its interrupt and DMA request signals

are routed through the ASC module.

This section presents an overview of the bus protocol, and its implementation by the ACB module.

•

ACCESS.bus master and slave

•

Supports polling and interrupt-controlled operation

•

Generate a wake-up signal on detection of a Start Condition, while in power-down mode

•

Optional internal pullup on SDA and SCL pins

•

Interrupt and DMA capability

•

Up to 400 kHz bus clock frequency (Fast-mode)

29.1 ACCESS.bus Protocol Overview

The ACCESS.bus protocol uses a two-wire interface for bi- directional communication between the

devices connected to the bus. The two interface signals are the Serial Data Line (SDA) and the Serial

Clock Line (SCL). These signals should be connected to the positive supply, through pullup resistors, to

keep the signals high when the bus is idle.

The ACCESS.bus protocol supports multiple master and slave transmitters and receivers. Each bus

device has a unique address and can operate as a transmitter or a receiver (though some peripherals are

only receivers).

Dual ACCESS.bus Interfaces

295

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