LM97600CIUTSLASHNOPB datasheet(29/58 Pages) TI1

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LM97600

www.ti.com

SNAS600A – JULY 2012 – REVISED MARCH 2013

FUNCTIONAL DESCRIPTION

The LM97600 is a versatile A/D Converter with an innovative architecture permitting very high speed operation.

The controls available ease the application of the device to circuit solutions. Optimum performance requires

adherence to the provisions discussed here and in the Applications Information section.

OVERVIEW

The LM97600 uses a calibrated folding and interpolating architecture that achieves 7.0 effective bits at sampling

rates up to 5.0 GS/s.

One clock input serves all converters. Special clock duty-cycle correction and alignment circuitry plus a high-

bandwidth input signal MUX allows the user to operate the four converters in the following three configurations:

•

Four converters operated independently (Input 1 to Channel A, Input 2 to Channel C, etc.)

•

Two groups of two converters interleaved into two independent channels (Input 1 or 2 to Channel A+C; and

Input 3 or 4 to Channel B+D)

•

Four converters interleaved into one channel with one input

Channel labels A, B, C, D indicate the time-order of sampling by the four converters when interleaved. Note that

each of the four ADCs is made up of two interleaved sub-ADCs, for a total of eight sub-ADCs. The outputs of

these sub-ADCs must be interleaved at the receiver in the proper order to re-create the sampled data sequence.

The digital output samples are 8B/10B encoded and serialized before being driven out at a maximum of 5-Gbps

per lane. Each 7 or 8 bit sample (see below for explanation of sample size) is encoded to a 10-bit, dc-balanced

word, and mapped to output lanes 1 to 10 in succession. Encoding and mapping is independent of whether the

device is operating as a single, dual, or quad ADC.

Selective Truncation

Each of the eight interleaved sub-ADCs digitizes its analog input to 8-bit resolution at a rate equal to 1/4th the

input clock rate (or 1/8th the fully-interleaved sample rate). The output of each sub-ADC is then truncated to 7-

bits for three out every eight consecutive samples. In a truncated sample the least-significant-bit (LSB) is forced

to zero.

Table 1. Truncation Pattern

Sample Number

n+1

n+2

n+3

n+4

n+5

n+6

n+7

LSB Truncated

Digital Word Size

Each of the eight sub-ADCs has its own divide-by-N (N=26) counter incrementing once every clock cycle. The

fixed truncation pattern shown above repeats continuously, but is delayed by one clock cycle every time the

counter reaches a pre-programmed value. The value that causes the pattern to delay is unique for each sub-

ADC, which reduces the occurrence of long, contiguous sequences of truncated words. Data is not truncated

when the pattern is delayed.

For N=26, there are (5/8 * 26) = 16.25 non-truncated words every 27 samples. On average this equates to (16.25

/ 27) = 0.601 (rounded to 0.6) valid bits in the LSB position at the interleaved sample rate.

The initial value of each of the eight counters is determined at power-up through a combination of random noise

and part-to-part process variation. Since each sub-ADC truncates its data at unpredictable points in time, it is not

possible to under-sample the output data stream at pre-determined instants to obtain only non-truncated data.

Table 2. Example Truncation Pattern With Delay

Sample Number

Divide by N count

Delay triggered

LSB truncated

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