LM97600CIUTSLASHNOPB datasheet(43/58 Pages) TI1

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LM97600

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SNAS600A – JULY 2012 – REVISED MARCH 2013

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, no input should go

more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits on even a

transient basis may not only cause faulty or erratic operation, but may impair device reliability. It is not

uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground.

Controlling the impedance of high speed lines and terminating these lines in their characteristic impedance

should control overshoot.

Care should be taken not to overdrive the inputs of the LM97600. Such practice may lead to conversion

inaccuracies and even to device damage.

Incorrect analog input common mode voltage in the d.c. coupled mode. As discussed in The Analog Inputs

and THE ANALOG INPUT sections, the Input common mode voltage (VCMI) must remain the specified range as

referenced to VCMO, which has a variability with temperature that must also be tracked. Distortion performance

will be degraded if the input common mode voltage is outside the specified VCMI range.

Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier

to drive the LM97600 as many high speed amplifiers will have higher distortion than will the LM97600, resulting

in overall system performance degradation.

Driving the clock input with an excessively high level signal. The ADC input clock level should not exceed

the level described in the Operating Ratings table or the input offset could change.

Inadequate input clock levels. As described in THE SAMPLE CLOCK INPUT, insufficient input clock levels can

result in poor performance. Excessive input clock levels could result in the introduction of an input offset.

Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having

other signals coupled to the input clock signal trace. This will cause the sampling interval to vary, causing

excessive output noise and a reduction in SNR performance.

Failure to provide adequate heat removal. As described in Thermal Management, it is important to provide

adequate heat removal to ensure device reliability. This can be done either with adequate air flow or the use of a

simple heat sink built into the board. The backside pad should be grounded for best performance.

Table 11. Register Addresses

4-Bit Address

Loading Sequence:

A4 loaded after H0, A0 loaded last

Hex

01h

Config 1

02h

Config 2

03h

Calibration Config

04h

Ch A Gain & Config

05h

Ch A Offset

06h

Ch B Gain & Config

07h

Ch B Offset

08h

Ch C Gain & Config

09h

Ch C Offset

0Ah

Ch D Gain & Config

0Bh

Ch D Offset

0Ch

Aperture Adjust

0Dh

ADC Test Pattern

0Eh

Cal Scan Register

0Fh

Reserved

10h

SYNC

11h

Serial Config 1

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