LM97600CIUTSLASHNOPB datasheet(52/58 Pages) TI1

52 / 58 page

LM97600

SNAS600A – JULY 2012 – REVISED MARCH 2013

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Table 29. Serial Config 2

Addr: 12h (1 0010b)

POR state: 0000h

Bit

D15

D14

D13

D12

D11

D10

Name

TT1[5:0]

TT0[9:0]

POR

Bits15:10

Test Table 1 (Lower 6 LSBits)

These bits set the lower 6 least significant bits of Test Lookup Table 1.

Bits 9:0

Test Table 0

These bits set the 10 bits of Test Lookup Table 0.

Table 30. Serial Config 3

Addr: 13h (1 0011b)

POR state: 0000h

Bit

D15

D14

D13

D12

D11

D10

Name

Res

DTP

TT2[9:0]

TT1[9:6]

POR

Bit 15

Reserved

Must be set to 0b.

Bit 14

Disable Training Pattern

When set to 1b, the SYNC pin will not put the encoder in training pattern mode. Useful to allow reading of divide-by-4 counter

state using SYNC pin without putting the part into training mode.

Bits 13:4

Test Table 2

These bits set the 10 bits of Test Lookup Table 2.

Bits 3:0

Test Table 1 (Upper 4 MSBits)

These bits set the 4 most significant bits of Test Lookup Table 1.

Table 31. Serial Config 4

Addr: 14h (1 0100b)

POR state: 4000h

Bit

D15

D14

D13

D12

D11

D10

Name

PDO

SPD

TT3[9:0]

POR

Bit 15

Force Test

Forces 8B10B encoders to enter Test Table mode during chip calibration (forces TestMode[2] high).

With Test Table values set to all zeros, this should create less noise during calibration.

Bit 14

Power Down Over-Range

When set to 1b, powers down the two over-range output pairs.

Bit 13

Short Circuit Protection Disable

When set to 1b, disables the serial output driver short circuit protection.

Bits 12:10

Test Mode

Configures the serial output test modes as follows:

000 = Normal ADC mode

001 = LFSR — all lanes same

010 = LFSR — all lanes different, offset = 10 bits lane to lane

011 = LFSR — all lanes different, offset = 50 bits lane to lane

For the LFSR offsets, lane_n(t) will have the same pattern as lane_n+1(t+offset)

100 = Table Mode 0

101 = Table Mode 1

In Table Mode 0, each 10 bit data value is output from MSb to LSb and all the inputs are output in the

order Test Table 0 to Test Table 3. In addition, the TestLane[9:0] settings allow individual lanes to be

disabled, by setting the appropriate TestLane[n] bit = 1.

In Table Mode 1 the TestLane[9:0] values select one of two sequences to be output on each lane. If

TestLane[n] = 0, the lane outputs data from Test Table 0 and Test Table 1. If TestLane[n]=1, the lane

outputs data from Test Table 2 and Test Table 3.

110 = Unused

111 = Unused

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