LM97600CIUTSLASHNOPB datasheet(30/58 Pages) TI1

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LM97600

SNAS600A – JULY 2012 – REVISED MARCH 2013

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Calibration

A calibration is performed upon power-up and can also be invoked by the user upon command. Calibration trims

the INx and CLK input differential termination resistors and minimizes full-scale error, offset error, DNL and INL,

resulting in maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal bias currents are also set with the

calibration process. All of this is true whether the calibration is performed upon power up or is performed upon

command. Running the calibration is an important part of this chip's functionality and is required in order to obtain

adequate performance. In addition to the requirement to be run at power-up, calibration must be re-run by the

user whenever the input Full Scale Range is changed significantly. For best performance, we recommend an on

command calibration be run after initial power up and the device has reached a stable temperature. Also, we

recommend that an on command calibration be run whenever the operating temperature changes significantly

relative to the specific system performance requirements.

In normal operation, calibration is performed just after application of power and whenever a valid calibration

command is given, which is holding the CAL pin low for at least 80 input clock cycles, then hold it high for at

least another 80 input clock cycles. The time taken by the calibration procedure is specified in the A.C.

Characteristics table. Holding the CAL pin high during power up will prevent the calibration process from running

until the CAL pin experiences the above-mentioned 80 input clock cycles low followed by 80 cycles high.

The CAL bit does not reset itself to zero automatically, but must be manually reset before another calibration

event can be initiated. If no further calibration event is desired, the CAL bit may be left high indefinitely, with no

negative consequences.

Acquiring the Input

Depending on operating mode, data is acquired at the rising, or both the rising and falling edges of CLK and the

digital equivalent of that data is available in the serialized data stream 38 to 42 input clock cycles later.

The LM97600 will convert as long as the input clock signal is present. The fully differential comparator design

and the innovative design of the sample-and-hold amplifier, together with calibration, enables very good

SINAD/ENOB response beyond 1.5 GHz. The LM97600 output data signaling is serialized LVDS and the data is

encoding is offset binary.

Configuration and Control

The LM97600 configuration and control is achieved via a number of logic input pins in combination with a

number configuration registers accessed via a serial interface. For more details refer to the DEVICE CONTROL

section.

The Analog Inputs

The LM97600 must be driven with a differential input signal. Operation with a single-ended signal is not

recommended as performance will suffer. It is important that the input signals are either a.c. coupled to the inputs

(Configuration Register 1 Bit 5 = 0), or d.c. coupled (Configuration Register 1, Bit 5 = 1). An input common mode

voltage equal to the VCMO output must be provided when d.c. coupling is used.

The full-scale input range for each converter can be set to values between 560 mVP-P and 840 mVP-P through the

serial interface. See THE ANALOG INPUT.

Clocking

The LM97600 sampling clock (CLK+/CLK-) must be driven with an a.c. coupled, differential clock signal. The

THE SAMPLE CLOCK INPUT section describes the use of the clock input pins.

The sampling clock CLK has duty cycle correction as part of its circuit. This circuitry allows the ADC to be

clocked with a signal source having a duty cycle of 70 to 30 % (worst case).

The LVDS Outputs

The data outputs (DS#) and Out Of Range (ORAC, ORBD) are LVDS. The differential output voltage swing is set

via the Output Voltage Select setting in Serial Config 1, Bits 11:10. The default setting of 400 mVp-p should work

for typical short distance interfaces. If large swings are necessary to compensate for additional distance, noise

pickup, etc., the output swing can be set as high as 800 mVp-p with a slight increase in device power

consumption.

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