LM97600CIUTSLASHNOPB datasheet(33/58 Pages) TI1

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LM97600

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SNAS600A – JULY 2012 – REVISED MARCH 2013

The ADC Mode (Quad/Dual/Single) does not change the mapping arrangement. Data is always mapped in the

above fashion. The mapped data is then 8b10b encoded and output on the 10 serial lanes. The 8b10b encoding

provides a number of specific benefits:

•

Standard encoding format, so IP is readily available in off-the-shelf FPGAs and ASIC building blocks

•

Inherent DC balance allows AC coupling of lanes with small on-chip capacitors

•

Inherent error checking

SYNC

The SYNC input is a differential LVDS logic input. To assert the SYNC input, a differential 1 is applied. To de-

assert SYNC a differential 0 must be applied. SYNC+/

− has an internal 100 ohm termination resistor and must

not be AC coupled.

Serial Data Training Sequence

The SYNC input performs two key functions. The primary function, discussed here, is to enable the output of the

serial data training pattern. This pattern is necessary to allow downstream deserializer circuitry to correctly

synchronize to the output data stream. Synchronization involves clock recovery as well as data word and frame

boundary location. Once this synchronization is established, the ADC can transition to outputting normal ADC

data. The SYNC input signal, when asserted, causes the ADC to begin outputting the training sequence. The

sequence is 8 characters long, twice the length of a data frame. The sequence is repeated indefinitely while the

SYNC input is asserted and is output on all 10 lanes simultaneously. The sequence follows below:

Table 5. Serial Data Training Sequence

Word

Character

K27.7

D5.6

K28.5

D5.6

K28.5

D5.6

K28.5

D5.6

K27.7 is a start symbol to help identify the start of frame. K28.5 is a comma symbol for alignment. D5.6 is a data

symbol with a lot of transitions to assist with bit alignment. When SYNC is de-asserted, an incomplete sync

frame will complete before outputting the first data frame.

Multiple ADC Synchronization

The second function for the SYNC input, is to facilitate the precise synchronization of multiple ADCs in a system.

The LM97600 input clock is internally process through a counter which creates a CLK/4 internal clocking system

fed to the 4 internal ADCs. To ensure synchronization between multiple LM97600 devices in a system, it is

important to align the CLK/4 counters in the multiple ADCs to the same divide by four state. The multiple ADC

synchronization features facilitate that process.

When SYNC is asserted, it is captured by the internal CLK signal and the state of the internal CLK/4 counter at

that instant is loaded in to bits-6:5 of the SYNC register. If the CLK and SYNC signals are fed into multiple

LM97600 at the same time, the relative state of the internal CLK/4 counters can be captured.

Once the relative CLK/4 states are known, it is then desired to adjust the phase of some of the LM97600 devices

until all CLK/4 counters are in the same state. Setting Configuration Register 4, bit-1 bumps or swallows one

input clock, causing the CLK/4 counter to shift one later with respect to other devices. Each time this bit is

changed from 0 to 1, the ADC will swallow one input clock, so it is a straightforward task to shift the CLK/4

counters until they are aligned.

One key challenge to making all of this work is ensuring that the SYNC inputs are captured by the input CLK in a

repeatable fashion. There are two key elements to ensuring this. First, the SYNC input must be created so that it

is synchronous to the input CLK, with a frequency relationship that is an integer multiple of CLK/4 (ie. CLK/8,

CLK/12, CLK/16, etc.) and a repeatable and fixed phase offset. Once this constraint is achieved it is easier to

capture it in a repeatable fashion. To further ease this task, the SYNC pulse is routed through a user adjustable

delay set via bits 15:7 of the SYNC register. This eases the timing requirements with respect to the input CLK

signal. As long as the SYNC pulse has a fixed timing relationship to the CLK rising edge, the internal delay can

be used to maximize the setup and hold times between the internally delayed SYNC, and the internal CLK

signal. These timing relationships are detailed in Figure 4 of the Timing Diagrams. The SYNC pulse must be of a

minimum width and its delayed assertion edge must observe setup and hold times with respect to the internal

CLK rising edge. Repetitive assertion of SYNC, and read back of the CLK/4 counter state will indicate if the

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