LM97600CIUTSLASHNOPB datasheet(11/58 Pages) TI1

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LM97600

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SNAS600A – JULY 2012 – REVISED MARCH 2013

Converter Electrical Characteristics (continued)

The following specifications apply after calibration for VA = VTH = VC = +1.2VDC, VO = V25 = +2.5VDC, VIN FSR (a.c. coupled) =

Default ECM setting, CL = 10 pF, Differential a.c. coupled Sinewave Input Clock, fCLK = 2.5 GHz at 0.5VP-P with 50% duty

cycle, REXT = 3600Ω ±0.1%, RTRIM = 3600Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential, after calibration.

Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.

(1)(2)

Typical

Limits

Units

Symbol

Parameter

Conditions

(3)

(Limits)

fIN = 248 MHz, VIN = FSR − 0.5 dB

SFDR

Spurious-Free dynamic Range

fIN = 998 MHz, VIN = FSR − 0.5 dB

ANALOG INPUT AND REFERENCE CHARACTERISTICS

mVP-P

490

(min)

Min FSR Setting

560

mVP-P

610

(max)

VIN

Full Scale Analog Differential Input Range

mVP-P

760

(min)

Max FSR Setting

850

mVP-P

930

(max)

Differential

0.08

CIN

Analog Input Capacitance(5)

Each input pin to ground

2.2

Ω (min)

RIN

Differential Input Resistance

100

107

Ω (max)

ANALOG OUTPUT CHARACTERISTICS(VCMO, VBG)

1.16

V (min)

VCMO

Common Mode Output Voltage

ICMO = ±100 µA

1.26

1.36

V (max)

Common Mode Output Voltage Temperature

TC VCMO

TA = −40°C to +85°C

(6)

118

ppm/°C

Coefficient

CLOAD

Maximum VCMO load Capacitance

See (7)

pF (min)

VCMO

1.0

V (min)

VBG

Bandgap Reference Output Voltage

IBG = ±100 µA

1.1

1.2

V (max)

TA = −40°C to +85°C,

TC VBG

Bandgap Reference Voltage Temperature Coefficient

ppm/°C

IBG = ±100 µA

(6)

CLOAD VBG Maximum Bandgap Reference load Capacitance

See (7)

pF (min)

TEMPERATURE DIODE CHARACTERISTICS

192 µA vs. 12 µA,

71.23

TJ = 25°C

ΔVBE

Temperature Diode Voltage

192 µA vs. 12 µA,

85.54

TJ = 85°C

LVDS INPUT CHARACTERISTICS(CLK+/-, SYNC+/-)

VP-P

0.4

(min)

Sine Wave Clock

0.6

2.0

VP-P

(max)

VID

Differential Clock Input Level(8)

VP-P

0.4

(min)

Square Wave Clock

0.6

2.0

VP-P

(max)

Differential

0.02

CIN

Input Capacitance(7)

Each input to ground

1.5

(5)

This parameter is ensured by design and is not tested in production.

(6)

This parameter is ensured by design and/or characterization and is not tested in production.

(7)

This parameter is ensured by design and is not tested in production.

(8)

The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated

from the die capacitances by lead and bond wire inductances.

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