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LM97600CIUT/NOPB Datasheet(PDF) 32 Page - Texas Instruments |
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LM97600CIUT/NOPB Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 58 page  8-BIT ADC_C 8b10b Encoder 8-BIT ADC_D Data Serializer 8 8 8-BIT ADC_A 8-BIT ADC_B Data Bus Output 10 Lanes High Speed Serial Lane 9 Lane 10 Lane 8 Lane 7 Lane 6 Lane 5 Lane 4 Lane 3 Lane 2 Lane 1 8 8 8 to 10 Lane Mapping LM97600 SNAS600A – JULY 2012 – REVISED MARCH 2013 www.ti.com SERIAL OUTPUT DATA FORMATTING ADC data is generated by the 4 internal ADCs. Each ADC generates a current and a delayed (sampled earlier in time) sample. For exampled, converter A outputs a normal A sampled, and an Ad delayed sample simultaneously. The outputs of all 4 converters (4 current and 4 delayed samples) are transferred to 8b10b encoder blocks. To keep the sampling clock and output data clock operating at the same frequency, it is easiest to have 10 lanes of data output . To accomplish this, the ADC output data is mapped into a frame which is 4 samples long and 10 lanes wide. This mapping function is performed before 8b10b encoding and serialization. Figure 40. ADC Data Flow The mapping sequence is shown below: Table 4. Output Data Mapping Lane Word 1 Word 2 Word 3 Word 4 Word 5 Frame 1 Frame 2... 1 Ad_1 Cd_2 A_3 C_4 Ad_6 2 Bd_1 Dd_2 B_3 D_4 Bd_6 3 Cd_1 A_2 C_3 Ad_5 Cd_6 4 Dd_1 B_2 D_3 Bd_5 Dd_6 5 A_1 C_2 Ad_4 Cd_5 A_6 6 B_1 D_2 Bd_4 Dd_5 B_6 7 C_1 Ad_3 Cd_4 A_5 C_6 8 D_1 Bd_3 Dd_4 B_5 D_6 9 Ad_2 Cd_3 A_4 C_5 Ad_7 10 Bd_2 Dd_3 B_4 D_5 Bd_7 32 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM97600 |
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