ADT7476AARQZ-R datasheet(48/69 Pages) ONSEMI

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ADT7476A

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Fan Sync

When two ADT7476As are used in a system, it is possible

to synchronize them so that one PWM channel from each

device can be effectively OR’ed together to create a PWM

output that reflects the maximum speed of the two OR’ed

PWMs. This OR’ed PWM can in turn be used to drive a

chassis fan.

Standby Mode

The ADT7476A has been specifically designed to

respond to the STBY supply. In computers that support S3

and S5 states, the core voltage of the processor is lowered in

these states. When monitoring THERM, the THERM timer

should be disabled during these states.

When the VCCP voltage drops below the VCCP low limit,

the following occurs:

1. Status Bit 1 (VCCP) in Interrupt Status Register 1

is set.

2. SMBALERT is generated, if enabled.

3. THERM monitoring is disabled. The THERM

timer should hold its value prior to the S3 or S5

state.

Once the core voltage, VCCP, goes above the VCCP low

limit, everything is re-enabled and the system resumes

normal operation.

XNOR Tree Test Mode

The ADT7476A includes an XNOR tree test mode. This

mode is useful for in-circuit test equipment at board-level

testing. By applying stimulus to the pins included in the

XNOR tree, it is possible to detect opens, or shorts, on the

system board.

The XNOR tree test is invoked by setting Bit 0 (XEN) of

the XNOR Tree Test Enable Register (0x6F).

Figure 66 shows the signals that are exercised in the

XNOR tree test mode.

Figure 66. XNOR Tree Test

TACH1

TACH2

TACH3

TACH4

PWM2

PWM3

PWM1/XTO

VID4

VID3

VID2

VID1

VID0

Power-On Default

When the ADT7476A is powered up, monitoring is off by

default and the PWM outputs go to 100%. All necessary

registers then need to be configured via the SMBus for the

appropriate functions to operate.

ADT7476AARQZ-R Datasheet(PDF) 48 Page - ON Semiconductor

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