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ADT7476AARQZ-R Datasheet(PDF) 56 Page - ON Semiconductor

Part # ADT7476AARQZ-R
Description  Remote Thermal Controller and Voltage Monitor
PDF  69 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADT7476AARQZ-R Datasheet(HTML) 56 Page - ON Semiconductor

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Table 62. TEMPERATURE LIMIT REGISTERS (Note 1)
Register Address
R/W
Description (Note 2)
Power-On Default
0x4E
R/W
Remote 1 Temperature Low Limit
0x81
0x4F
R/W
Remote 1 Temperature High Limit
0x7F
0x50
R/W
Local Temperature Low Limit
0x81
0x51
R/W
Local Temperature High Limit
0x7F
0x52
R/W
Remote 2 Temperature Low Limit
0x81
0x53
R/W
Remote 2 Temperature High Limit
0x7F
1. Exceeding any of these temperature limits by 1
°C causes the appropriate status bit to be set in the interrupt status register. Setting the
Configuration Register 1 Lock bit has no effect on these registers.
2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value
is equal to or below its low limit (
≤ comparison).
Table 63. FAN TACH LIMIT REGISTERS (Note 1)
Register Address
R/W
Description
Power-On Default
0x54
R/W
TACH1 Minimum Low Byte
0xFF
0x55
R/W
TACH1 Minimum High Byte/Single-channel
ADC Channel Select
0xFF
0x56
R/W
TACH2 Minimum Low Byte
0xFF
0x57
R/W
TACH2 Minimum High Byte
0xFF
0x58
R/W
TACH3 Minimum Low Byte
0xFF
0x59
R/W
TACH3 Minimum High Byte
0xFF
0x5A
R/W
TACH4 Minimum Low Byte
0xFF
0x5B
R/W
TACH4 Minimum High Byte
0xFF
1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set
in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 Lock bit has no effect on these registers.
Table 64. REGISTER 0x55 − TACH1 MINIMUM HIGH BYTE (POWER-ON DEFAULT = 0xFF)
Bit No.
Mnemonic
R/W
Description
[4:0]
Reserved
Read-only
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits
are reserved. Otherwise, these bits represent Bits [4:0] of the TACH1 minimum high byte.
[7:5]
SCADC
R/W
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits
are used to select the only channel from which the ADC will take measurements. Otherwise,
these bits represent Bits [7:5] of the TACH1 minimum high byte.



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