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ADT7476AARQZ-R Datasheet(PDF) 22 Page - ON Semiconductor |
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ADT7476AARQZ-R Datasheet(HTML) 22 Page - ON Semiconductor |
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22 / 69 page ![]() ADT7476A www.onsemi.com 22 Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any way. Status Registers The results of limit comparisons are stored in Interrupt Status Register 1 and Interrupt Status Register 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is out-of-limits, the corresponding status register bit is set to 1. The state of the various measurement channels can be polled by reading the status registers over the serial bus. In Bit 7 (OOL) of Interrupt Status Register 1 (0x41), 1 means an out-of-limit event has been flagged in Interrupt Status Register 2. This means the user also needs to read Interrupt Status Register 2. Alternatively, Pin 10 or Pin 14 can be configured as an SMBALERT output. This hard interrupt automatically notifies the system supervisor of an out-of-limit condition. Reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Status register bits are sticky. Whenever a status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). The only way to clear the status bit is to read the status register after the event has gone away. Interrupt mask registers (0x74 and 0x75) allow individual interrupt sources to be masked from causing an SMBALERT. However, if one of these masked interrupt sources goes out of limit, its associated status bit is set in the status registers. Table 28. INTERRUPT STATUS REGISTER 1 (0x41) Bit Mnemonic Description [7] OOL 1 denotes a bit in Interrupt Status Register 2 is set and Interrupt Status Register 2 should be read. [6] R2T 1 indicates that the Remote 2 Temperature High or Low limit has been exceeded. [5] LT 1 indicates that the Local Temperature High or Low Limit has been exceeded. [4] R1T 1 indicates that the Remote 1 Temperature High or Low Limit has been exceeded. [3] 5.0 V 1 indicates that the 5.0 V High or Low Limit has been exceeded. [2] VCC 1 indicates that the VCC High or Low Limit has been exceeded. [1] VCCP 1 indicates that the VCCP High or Low Limit has been exceeded. [0] 2.5 V 1 indicates that the 2.5 V High or Low Limit has been exceeded. If the 2.5 V input is configured as THERM, this bit represents the status of THERM. Table 29. INTERRUPT STATUS REGISTER 2 (0x42) Bit Mnemonic Description [7] D2 1 indicates an open or short on D2+/D2− inputs. [6] D1 1 indicates an open or short on D1+/D1− inputs. [5] F4P 1 indicates Fan 4 has dropped below minimum speed. Alternatively, indicates that the THERM limit has been exceeded, if the THERM function is used. Alternatively, indicates the status of GPIO6. [4] FAN3 1 indicates that Fan 3 has dropped below minimum speed. [3] FAN2 1 indicates that Fan 2 has dropped below minimum speed. [2] FAN1 1 indicates that Fan 1 has dropped below minimum speed. [1] OVT 1 indicates that a THERM overtemperature limit has been exceeded. [0] 12 V/VC 1 indicates a 12 V high or low limit has been exceeded. If the VID code change function is used, this bit indicates a change in VID code on the VID0 to VID4 inputs. SMBALERT Interrupt Behavior The ADT7476A can be polled for status, or an SMBALERT interrupt can be generated for out-of-limit conditions. It is important to note how the SMBALERT output and status bits behave when writing interrupt handler software. Figure 29. SMBALERT and Status Bit Behavior HIGH LIMIT TEMPERATURE “STICKY” STATUS BIT SMBALERT CLEARED ON READ (TEMP BELOW LIMIT) TEMP BACK IN LIMIT (STATUS BIT STAYS SET) HIGH LIMIT TEMPERATURE “STICKY” STATUS BIT SMBALERT Figure 29 shows how the SMBALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky because they remain set until read by software. This ensures that an out-of-limit event cannot be missed if the software is periodically polling the device. |
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