SPC564A80L7 datasheet(73/157 Pages) STMICROELECTRONICS

73 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Pinout and signal description

Doc ID 15399 Rev 9

73/157

2.5

Signal details

Table 5.

Pad types

Pad Type

Name

I/O Voltage Range

Slow

pad_ssr_hv

3.0V - 5.5 V

Medium

pad_msr_hv

3.0 V - 5.5 V

Fast

pad_fc

3.0 V - 3.6 V

MultiV(1),(2)

Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is

selected, otherwise they are high swing.

VDDEH7 supply cannot be below 4.5 V when in low-swing mode.

pad_multv_hv

3.0 V - 5.5 V (high swing mode)

3.0 V - 3.6 V (low swing mode)

Analog

pad_ae_hv

0.0 - 5.5 V

LVDS

pad_lo_lv

—

Table 6.

Signal details

Signal

Module or Function

Description

CLKOUT

Clock Generation

SPC564A80 clock output for the external/calibration bus

interface

ENGCLK

Clock Generation

Clock for external ASIC devices

EXTAL

Clock Generation

Input pin for an external crystal oscillator or an external clock

source based on the value driven on the PLLREF pin at reset.

PLLREF

Clock Generation

Reset/Configuration

PLLREF is used to select whether the oscillator operates in xtal

mode or external reference mode from reset. PLLREF=0

selects external reference mode. On the 324BGA package,

PLLREF is bonded to the ball used for PLLCFG[0] for

compatibility with previous devices .

For the 176-pin QFP and 208-ball BGA packages:

0: External reference clock is selected.

1: XTAL oscillator mode is selected

For the 324 ball BGA package:

If RSTCFG is 0:

0: External reference clock is selected.

1: XTAL oscillator mode is selected.

If RSTCFG is 1, XTAL oscillator mode is selected.

XTAL

Clock Generation

Crystal oscillator input

DSPI_B_SCK_LVDS-

DSPI_B_SCK_LVDS+

DSPI

LVDS pair used for DSPI_B TSB mode transmission

DSPI_B_SOUT_LVDS-

DSPI_B_SOUT_LVDS+

DSPI

LVDS pair used for DSPI_B TSB mode transmission

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