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SPC564A80L7 Datasheet(PDF) 78 Page - STMicroelectronics

Part # SPC564A80L7
Description  Up to 4 multiply and accumulate operations per cycle
PDF  157 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC564A80L7 Datasheet(HTML) 78 Page - STMicroelectronics

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Pinout and signal description
SPC564A74L7, SPC564A80B4, SPC564A80L7
78/157
Doc ID 15399 Rev 9
IRQ[0:5]
IRQ[7:15]
SIU - External
Interrupts
The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select
Register 1 is used to select the IRQ[0:15] pins as inputs to the
IRQs.
See the SPC564A80 Microcontroller Reference Manual for
more information.
NMI
SIU - External
Interrupts
Non-Maskable Interrupt
GPIO[0:3]
GPIO[8:43]
GPIO[62:65]
GPIO[68:70]
GPIO[75:145]
GPIO[179:204]
GPIO[208:213]
GPIO[219]
GPIO[244:245]
SIU - GPIO
Configurable general purpose I/O pins. Each GPIO input and
output is separately controlled by an 8-bit input (GPDI) or
output (GPDO) register. Additionally, each GPIO pins is
configured using a dedicated SIU_PCR register.
The GPIO pins are generally multiplexed with other I/O pin
functions.
See The SPC564A80 Microcontroller Reference Manual for
more information.
–
RESET
SIU - Reset
The RESET pin is an active low input. The RESET pin is
asserted by an external device during a power-on or external
reset. The internal reset signal asserts only if the RESET pin
asserts for 10 clock cycles. Assertion of the RESET pin while
the device is in reset causes the reset cycle to start over.
The RESET pin has a glitch detector which detects spikes
greater than two clock cycles in duration that fall below the
switch point of the input buffer logic of the VDDEH input pins.
The switch point lies between the maximum VIL and minimum
VIH specifications for the VDDEH input pins.
RSTCFG
SIU - Reset
Used to enable or disable the PLLREF and the BOOTCFG[0:1]
configuration signals.
0:Get configuration information from BOOTCFG[0:1] and
PLLREF
1:Use default configuration of booting from internal flash with
crystal clock source
For the 176-pin QFP and 208-ball BGA packages RSTCFG is
always 0, so PLLREF and BOOTCFG signals are used.
RSTOUT
SIU - Reset
The RSTOUT pin is an active low output that uses a push/pull
configuration. The RSTOUT pin is driven to the low state by the
MCU for all internal and external reset sources. There is a
delay between initiation of the reset and the assertion of the
RSTOUT pin.
1.
Do not connect pin directly to a power supply or ground.
Table 6.
Signal details (continued)
Signal
Module or Function
Description



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