SPC564A80L7 datasheet(14/157 Pages) STMICROELECTRONICS

14 / 157 page

Introduction

SPC564A74L7, SPC564A80B4, SPC564A80L7

14/157

Doc ID 15399 Rev 9

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4 slave ports

–Flash

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Calibration and EBI bus

–SRAM

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Peripheral bridge

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32-bit internal address, 64-bit internal data paths

1.5.3

eDMA

The enhanced direct memory access (eDMA) controller is a second-generation module

capable of performing complex data movements via 64 programmable channels, with

minimal intervention from the host processor. The hardware micro-architecture includes a

DMA engine which performs source and destination address calculations, and the actual

data movement operations, along with an SRAM-based memory containing the transfer

control descriptors (TCD) for the channels. This implementation is utilized to minimize the

overall block size. The eDMA module provides the following features:

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All data movement via dual-address transfers: read from source, write to destination

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Programmable source and destination addresses, transfer size, plus support for

enhanced addressing modes

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Transfer control descriptor organized to support two-deep, nested transfer operations

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An inner data transfer loop defined by a “minor” byte transfer count

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An outer data transfer loop defined by a “major” iteration count

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Channel activation via one of three methods:

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Explicit software initiation

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Initiation via a channel-to-channel linking mechanism for continuous transfers

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Peripheral-paced hardware requests (one per channel)

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Support for fixed-priority and round-robin channel arbitration

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Channel completion reported via optional interrupt requests

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One interrupt per channel, optionally asserted at completion of major iteration count

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Error termination interrupts optionally enabled

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Support for scatter/gather DMA processing

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Ability to suspend channel transfers by a higher priority channel

1.5.4

Interrupt controller

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt

requests, suitable for statically scheduled hard real-time systems.

For high priority interrupt requests, the time from the assertion of the interrupt request from

the peripheral to when the processor is executing the interrupt service routine (ISR) has

been minimized. The INTC provides a unique vector for each interrupt request source for

quick determination of which ISR needs to be executed. It also provides an ample number of

priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To

allow the appropriate priorities for each source of interrupt request, the priority of each

interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be

supported. The INTC supports the priority ceiling protocol for coherent accesses. By

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