SPC564A80L7 datasheet(15/157 Pages) STMICROELECTRONICS

15 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Introduction

Doc ID 15399 Rev 9

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providing a modifiable priority mask, the priority can be raised temporarily so that all tasks

which share the resource cannot preempt each other.

The INTC provides the following features:

●

9-bit vector addresses

●

Unique vector for each interrupt request source

●

Hardware connection to processor or read from register

●

Each interrupt source can assigned a specific priority by software

●

Preemptive prioritized interrupt requests to processor

●

ISR at a higher priority preempts executing ISRs or tasks at lower priorities

●

Automatic pushing or popping of preempted priority to or from a LIFO

●

Ability to modify the ISR or task priority to implement the priority ceiling protocol for

accessing shared resources

●

Low latency—three clocks from receipt of interrupt request from peripheral to interrupt

request to processor

This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and

multiplexing logic.

1.5.5

Memory protection unit (MPU)

The Memory Protection Unit (MPU) provides hardware access control for all memory

references generated in a device. Using preprogrammed region descriptors, which define

memory spaces and their associated access rights, the MPU concurrently monitors all

system bus transactions and evaluates the appropriateness of each transfer. Memory

references with sufficient access control rights are allowed to complete; references that are

not mapped to any region descriptor or have insufficient rights are terminated with a

protection error response.

The MPU has these major features:

●

Support for 16 memory region descriptors, each 128 bits in size

–

Specification of start and end addresses provide granularity for region sizes from

32 bytes to 4 GB

–

MPU is invalid at reset, thus no access restrictions are enforced

–

Two types of access control definitions: processor core bus master supports the

traditional {read, write, execute} permissions with independent definitions for

supervisor and user mode accesses; the remaining non-core bus masters (eDMA,

FlexRay, and EBI1) support {read, write} attributes

–

Automatic hardware maintenance of the region descriptor valid bit removes issues

associated with maintaining a coherent image of the descriptor

–

Alternate memory view of the access control word for each descriptor provides an

efficient mechanism to dynamically alter the access rights of a descriptor only(a)

–

For overlapping region descriptors, priority is given to permission granting over

access denying as this approach provides more flexibility to system software

●

Support for two XBAR slave port connections (SRAM and PBRIDGE)

–

For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware

monitors every port access using the pre-programmed memory region descriptors

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