SPC564A80L7 datasheet(11/157 Pages) STMICROELECTRONICS

11 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Introduction

Doc ID 15399 Rev 9

11/157

1.4

SPC564A80 feature list

●

150 MHz e200z4 Power Architecture core

–

Variable length instruction encoding (VLE)

–

Superscalar architecture with 2 execution units

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Up to 2 integer or floating point instructions per cycle

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Up to 4 multiply and accumulate operations per cycle

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Memory organization

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4 MB on-chip flash memory with ECC and Read While Write (RWW)

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192 KB on-chip SRAM with standby functionality (32 KB) and ECC

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8 KB instruction cache (with line locking), configurable as 2- or 4-way

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14 + 3 KB eTPU code and data RAM

–5

 4 crossbar switch (XBAR)

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24-entry MMU

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External Bus Interface (EBI) with slave and master port

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Fail Safe Protection

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16-entry Memory Protection Unit (MPU)

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CRC unit with 3 sub-modules

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Junction temperature sensor

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Interrupts

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Configurable interrupt controller (with NMI)

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64-channel DMA

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Serial channels

–3

 eSCI

–3

 DSPI (2 of which support downstream Micro Second Channel [MSC])

–3

 FlexCAN with 64 messages each

–1

 FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128

message objects and ECC

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 eMIOS: 24 unified channels

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 eTPU2 (second generation eTPU)

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32 standard channels

–1

 reaction module (6 channels with three outputs per channel)

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2 enhanced queued analog-to-digital converters (eQADCs)

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Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels

with external multiplexers

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6 command queues

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Trigger and DMA support

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688 ns minimum conversion time

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On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)

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Nexus

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Class 3+ for the e200z4 core

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Class 1 for the eTPU

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JTAG (5-pin)

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