SPC564A80L7 datasheet(100/157 Pages) STMICROELECTRONICS

100 / 157 page

Electrical characteristics

SPC564A74L7, SPC564A80B4, SPC564A80L7

100/157

Doc ID 15399 Rev 9

RPUPD5K

SR C

Weak Pull-Up/Down

Resistance(20),

 Option

5V±5%

supply

1.4

—

7.5



RPUPDMTCH

Pull-up/Down

Resistance matching

ratios (100K/200K)

Pull-up and

pull-down

resistances

both enabled

and settings are

equal.

–2.5

—

2.5

TA (TL to TH)SR —

Operating temperature

range - ambient

(packaged)

—

–40.0

125.0

C

—SR —

Slew rate on power

supply pins

——

V/ms

These specifications apply when VRC33 is supplied externally, after disabling the internal regulator (VDDREG = 0).

ADC is functional with 4 V

 V

DDA  4.75 V but with derated accuracy. This means the ADC will continue to function at full

speed with no undesirable behavior, but the accuracy will be degraded.

The VDDF supply is connected to VDD in the package substrate. This specification applies to calibration package devices

only.

VFLASH is only available in the calibration package.

Power supply for multi-voltage pads cannot be below 4.5 V when in low-swing mode.

The slew rate (SRC) setting must be 0b11 when in low-swing mode.

While in low-swing mode there are no restrictions in transitioning to high-swing mode.

Pin in low-swing mode can accept a 5 V input.

All VOL/VOH values 100% tested with ± 2 mA load except where noted.

10. Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code,

4 x ADC conversion every 10 ms, 2 x PWM channels 1 kHz, all other modules stopped.

11. Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped.

12. This current will be consumed for external regulation and internal regulation, when 3.3V regulator is switched off by shadow

flash

13. If 1.2V and 3.3V internal regulators are on,then iddreg=70mA

If supply is external that is 3.3V internal regulator is off, then iddreg=15mA

14. Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a

particular I/O segment, and the voltage of the I/O segment. See Table 22 for values to calculate power dissipation for

specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for

each pin on the segment.

15. Absolute value of current, measured at VIL and VIH.

16. Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to fast, slow, and medium pads.

17. Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for

each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to analog pads.

18. Applies to CLKOUT, external bus pins, and Nexus pins.

19. Applies to the FCK, SDI, SDO, and SDS pins.

20. This programmable option applies only to eQADC differential input channels and is used for biasing and sensor

diagnostics.

Table 21.

DC electrical specifications (continued)

Symbol

Parameter

Conditions

Value

Unit

min

typ

max

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