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SPC564A80L7 Datasheet(PDF) 74 Page - STMicroelectronics |
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SPC564A80L7 Datasheet(HTML) 74 Page - STMicroelectronics |
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74 / 157 page  Pinout and signal description SPC564A74L7, SPC564A80B4, SPC564A80L7 74/157 Doc ID 15399 Rev 9 DSPI_C_SCK_LVDS- DSPI_C_SCK_LVDS+ DSPI LVDS pair used for DSPI_C TSB mode transmission DSPI_C_SOUT_LVDS- DSPI_C_SOUT_LVDS+ DSPI LVDS pair used for DSPI_C TSB mode transmission PCS_B[0] PCS_C[0] PCS_D[0] DSPI_B - DSPI_D Peripheral chip select when device is in master mode—slave select when used in slave mode PCS_B[1:5] PCS_C[1:5] PCS_D[1:5] DSPI_B - DSPI_D Peripheral chip select when device is in master mode—not used in slave mode SCK_B SCK_C SCK_D DSPI_B - DSPI_D DSPI clock—output when device is in master mode; input when in slave mode SIN_B SIN_C SIN_D DSPI_B - DSPI_D DSPI data in SOUT_B SOUT_C SOUT_D DSPI_B - DSPI_D DSPI data out ADDR[10:31] EBI The ADDR[10:31] signals specify the physical address of the bus transaction. The 26 address lines correspond to bits 3-31 of the EBI’s 32-bit internal address bus. ADDR[15:31] can be used as Address and Data signals when configured appropriately for a multiplexed external bus. This allows 32-bit data operations, or 16-bit data operations without using DATA[0:15] signals. ALE EBI The Address Latch Enable (ALE) signal is used to demultiplex the address from the data bus. It is asserted while the least significant 16 bits of the address are present in the multiplexed address/data bus. BDIP EBI BDIP is asserted to indicate that the master is requesting another data beat following the current one. CS[0:3] EBI CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the Primary external bus. DATA[0:31] EBI The DATA[0:31] signals contain the data to be transferred for the current transaction. OE EBI OE is used to indicate when an external memory is permitted to drive back read data. External memories must have their data output buffers off when OE is negated. OE is only asserted for chip-select accesses. Table 6. Signal details (continued) Signal Module or Function Description |
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