SPC564A80L7 datasheet(85/157 Pages) STMICROELECTRONICS

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SPC564A74L7, SPC564A80B4, SPC564A80L7

Electrical characteristics

Doc ID 15399 Rev 9

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3.3.1

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

Equation 1 TJ = TA + (RJA * PD)

where:

TA = ambient temperature for the package (

oC)

RJA = junction-to-ambient thermal resistance (

oC/W)

PD = power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards

to provide consistent values for estimations and comparisons. The difference between the

values determined for the single-layer (1s) board compared to a four-layer board that has

two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal

resistance is not a constant. The thermal resistance depends on the:

●

Construction of the application board (number of planes)

●

Effective size of the board which cools the component

●

Quality of the thermal and electrical connections to the planes

●

Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using

fewer vias to connect the package to the planes reduces the thermal performance. Thinner

planes also reduce the thermal performance. When the clearance between the vias leave

the planes virtually disconnected, the thermal performance is also greatly reduced.

Table 12.

Thermal characteristics for 324-pin PBGA(1)

Symbol

Parameter

Conditions

Value

Unit

RJA

D Junction-to-Ambient, Natural Convection(2)

Single layer board - 1s

°C/W

RJA

D Junction-to-Ambient, Natural Convection(2)

Four layer board - 2s2p

°C/W

RJMA

D Junction-to-Moving-Air, Ambient(2)

at 200 ft./min., single

layer board

°C/W

RJMA

D Junction-to-Moving-Air, Ambient(2)

at 200 ft./min., four layer

board 2s2p

°C/W

RJB

D Junction-to-Board(3)

°C/W

RJCtop

D Junction-to-Case(4)

7°C/W



Junction-to-Package Top, Natural

Convection(5)

2°C/W

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification

for the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

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