EM6812F2TP24B datasheet(46/81 Pages) EMMICRO

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EM6812

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11.4.2 SPI outputs

SPI: SOUT, SCLK (in master mode)

Table 42. Port B settings for SPI outputs

SPI output terminals

−

SOUT

−

SCLK in master mode

Notes

Output mode, CMOS high drive

SOUT

SCLK

SPI outputs

Output mode, NCH open drain

0 / High-Z

SPI outputs,

needs external pull-up

Output mode, NCH open drain, Pull-up

0 / Weak Hi

SPI outputs, pull-up intern

11.4.3 SPI inputs

SPI: SIN, SCLK (in slave mode)

Table 43. Port B settings for SPI inputs.

SPI input terminals

−

SIN

−

SCLK in slave mode

Notes

SCLK, SIN input

High-Z

No pull, Terminals must be driven

externally

SCLK, SIN input with pull-up

Weak Hi

Pull-up has priority

SCLK, SIN input with pull-down

Weak Lo

Default state after Power-up

11.4.4 Dual Port RAM terminals

Dual Port Ram output (while EnDualRAM=’1’, ExtCEn=’1’, ExtWrEn=’0’)

Table 44. Port B settings for DPR outputs

Dual Port RAM data output

−

DPData[7:0]

Notes

Output mode, CMOS high drive

DPData

DP outputs

Output mode, NCH open drain

0 / High-Z

DP outputs,

needs external pull-up

Output mode, NCH open drain, Pull-up

0 / Weak Hi

DP outputs, pull-up intern

In all other Dual Port Ram cases (not during read access), the port B terminals are configured based on the normal mode

bit settings. The only difference is that the port B inputs must not be left floating.

EM6812F2TP24B Datasheet(PDF) 46 Page - EM Microelectronic - MARIN SA

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