EM6812F2TP24B datasheet(58/81 Pages) EMMICRO

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EM6812

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In Zero-Stop mode the PWM becomes '0' and stops after zero detection. See below.

Figure 35. PWM or Frequency generations in Zero-Stop mode.

13.2.6.1 Frequency and Duty cycle Calculation

100

TimXLoad

TimXComp

DutyCyle

(TimXLoad

ClkTim

PWM

⋅

13.2.6.2 Frequency generation

Frequency generation is an extension of the PWM function. The only difference is that in Frequency generation the duty

cycle and the signal period both change. The period adjustment is made with the autoreload load value. Whenever the load

value is changed, it will be applied on the next following loop after the zero crossing.

13.2.7 16-bits configuration

Timer1 and timer2 can form together a 16-bit timer12. So can timer3 and timer4 which form timer34. In this configuration,

timer1 (or timer3) becomes the master configuration for start source, clock source, the PWM mode, Auto-Reload or Zero-

Stop mode and IRQ selection.

The LSB comes from the timer1 and timer3 and the MSB from timer2 and timer4.

The functionality remains identical to the standalone 8-bit timers but the load, compare and status values are split in two

registers: RegTimXStatus, RegTimXLoad and RegTimXComp.

To merge timer1 and timer2 the bit EnTim12 in RegTimersCfg must be set at ‘1’.

To merge timer3 and timer4 the bit EnTim34 in RegTimersCfg must be set at ‘1’.

With timers merged the specific selection bits for timer2 or 4 have no function anymore and the interrupt source from the

slave timers (2 or 4) will be inactive.

ClkIn

SwStartX

TimXLoad

TimXComp

PWMX

TimXStatus

EM6812F2TP24B Datasheet(PDF) 58 Page - EM Microelectronic - MARIN SA