EM6812F2TP24B datasheet(13/81 Pages) EMMICRO

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5.2

General Purpose Registers, 16 Bytes

A total of 16 general purpose 8-bit registers are available. 12 of these registers are realized as low power RAM to store and

recall frequently accessed variables with minimum power whereas the power saving is realized by minimizing the parasitic

capacitance which are inherent to large memories. The other 4 bytes are shared with the Dual Port RAM function. These

registers are reset to ‘00’ by POR only.

Table 8. General purpose register mapping

Name

Res

Dec

Hex

LPRam0

0000

0x0000

…

Low Power RAM

(General purpose

registers)

LPRAM11

0011

0x000B

DPRam0

0012

0x000C

…

LP Ram shared with

Dual Port RAM

DPRam3

0015

0x000F

Direct and

indexed

addressing

5.3

Dual Port RAM (DPR)

The DPR is a memory block, which allows data, read and write, accesses from either the CPU core or an external

processor in a total asynchronous way. The Dual Port RAM external data IO is mapped on Port B, the control signals on

Port A. The occurrence of possible access conflicts is flagged to the CPU with 2 Interrupts. Priority is given to the external

access.

Table 9. DPR Port mapping

DP RAM external connection

Port mapping

Function

ExtDat[7:0]

PB[7:0]

External bi-directional data bus

ExtAddr[1:0]

PA[3:2]

External address

ExtWen

PA[1]

External write or read access selector

ExtCen

PA[0]

External chip enable, validates the access

Setting the bit EnDualRam = ‘1’ in register RegCfgPB enables the DPR function. It is still possible to use the Port B as a

standard port even if the DPR function is enabled. Only while input ExtWen is low and ExtCen is high the port B is forced as

output. In all other cases the port B configuration is given as defined by the port B configuration registers. Please refer also

to the port B description.

The terminal configuration of the DPR control inputs on port A is totally free.

Note:

The port B terminals must not be left floating while EnDualRam=’1’. One may use the integrated pull resistors if the drive

conditions are not sure.

5.3.1

CPU R/W access to DPR

CPU Read and Write access are performed in the same way as for all other general-purpose registers. No special

precautions need to be done as long as EnDualRam is not set. When EnDualRam is set, conflicts with external access

may occur. Such conflicts are flagged with interrupts to the CPU. Refer to 5.3.4 Conflict handling.

Table 10. DPR memory address mapping

Bit_Names

ExtAddr[1:0]

on port A

Res

Reset by

Adr(Dec)

Adr(Hex)

DPRam0

DPR0[7:0]

POR

0x0C

DPRam1

DPR1[7:0]

POR

0x0D

DPRam2

DPR2[7:0]

POR

0x0E

DPRam3

DPR3[7:0]

POR

0x0F

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