EM6812F2TP24B datasheet(22/81 Pages) EMMICRO

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7.6

Watchdog

The digital watchdog is part of the integrated safety functions. Its main task is to supervise the good firmware execution

flow. As such it may prevent being stuck in an unwanted endless loop or may allow system recovery in other cases. Its

implementation is realised with a low speed counter, which asserts a reset signal on overrun.

Watchdog reset is flagged with bit ResetWDFlag in register RegResStat. It may be used to localize the reset source. Write

‘0’ to clear.

The firmware must regularly clear the watchdog otherwise a watchdog reset will occur at timer overrun, this watchdog reset

will itself trigger a system reset and forces the circuit to restart.

The watchdog function is always enabled after start-up and after any reset.

The watchdog is configurable

•

1Hz or 128Hz clock sources (timeouts of ~4s or ~30ms)

•

Secure watchdog disabling (locking) with special watchdog

•

Reading of the 2 bit watchdog counter value

7.6.1

Watchdog counter

To clear the watchdog counter the firmware must write the bit WDClear at ‘1’ in the register RegWDSys. In this way the 2

bits counter is reset and the watchdog restart from 0. WDClear is always read at ‘0’ and writing ‘0’ has no effect. It is

recommended to clear the WD counter frequently I.e. every 1s while working with the 1Hz counter clock source.

Figure 14. Watchdog timing diagram

The watchdog counter status is accessible by reading WDVal[1:0] in RegWDSys. These two bits are not accessible in write

mode. The counter value is '0' if the WD is disabled.

With WDClkSel bit it is possible to select from 2 prescaler1 clock sources; Pr1Ck[0] (typ.1Hz) and Pr1ck[7] (typ.128Hz),

meaning that the watchdog time out is respectively ~4s and ~30ms.

Changing the prescaler1 input clock selection might also change the watchdog counter frequency.

7.6.2

Lock/Unlock

It is possible to disable the watchdog by in a save way to prevent that system malfunction can itself inhibit the WD.

Disabling needs to follow a strict protocol using key lock and key bits which at the end need to be confirmed with writing the

EnWD

at ‘0’.

The key lock system WDKeyLock[2:0] in RegWDSys allows the software writing the key word WDKey in the register

RegWDKey. It is possible to write EnWD at ‘0’ only when the watchdog key word has been loaded.

When the watchdog is disable, WDKey and WDKeyLock must not change; if one of them is modified or EnWD is written at

'1' the watchdog is directly enabled.

Note:

EnWD can not be written '0' as long as the valid key lock number and the valid key word are not set.

When WDKeyLock is not the valid number, the WDKey is reset and can not be changed.

How to Unlock (Disable the watchdog)

st: Write the valid key lock number hex47 in RegWDSys

nd: Write the valid key word hex96 in register RegWDKey

rd: Disable the WD by writing hex 07 in register RegWDSys

How to Lock (Enable the watchdog)

Locking by clearing the WDKeyLock.

This action will automatically also clear WDKey and EnWD bits.

WDReset

WDClk0

WDVal[1:0]

ResSys

System cold start

RC cold start

EM6812F2TP24B Datasheet(PDF) 22 Page - EM Microelectronic - MARIN SA

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