EM6812F2TP24B datasheet(20/81 Pages) EMMICRO

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EM6812

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7.3

Reset Pad

A high level on RESET terminal will trigger a system reset. All registers except the ones connected to POR will be

initialized with the reset input. A pull-down resistor is connected on this terminal.

The input may be debounced with either a high or low frequency clock. This reset terminal may be disabled if not desired

with bit DisResInp located in RegSys1. In the default configuration the reset input is directly routed to the reset controller.

The Reset occurance is flagged with bit ResetPadFlag in register RegResStat. Write ‘0’ to clear.

Figure 10. Reset terminal architecture

With the debouncer, EnDebResPad = ‘1’, the reset input signal must remain high during 1 full debouncer clock cycle to

pass and eventually create the ResetPad signal. The high and low frequency debouncing clocks are issued from Prescaler1

(Pr1Ck[13], Pr1Ck[8]). The selection is performed with bit CkDebResPad in register in register RegResStat

7.4

PortA Input Reset

Single port A input states or port A combinations can be defined to trigger a system reset. This function can be inhibited

with bit DisResInp in register RegSys1. Please refer to the chapter PortA for the input reset combination set-up. The Reset

occurance is flagged with bit ResInpPAFlag in register RegResStat. Write ‘0’ to clear. The ResInpPAFlag will also show in

case of BrownOut reset when the DisResInp was set ‘1’.

Figure 11. PortA input reset

The ResInpPA signal, which is the output of the combination matrix, can be used debounced or straight as system reset.

High and low debouncing clock frequencies are selectable, both are issued from Prescaler1 (Pr1Ck[13], Pr1Ck[8]).

Debouncer and clock selections are performed with bit EnDebResInp and bit CkDebResInp in register RegCfgPA.

DebResetPad

Reset

8kHz

256Hz

Debouncer

ResSys

CkDebResPad

EnDebResPad

DebResInpPA

ResSys

8kHz

256Hz

ResInpPA

Debouncer

CkDebResInp

EnDebResInp

PortA

logic

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