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EM6812F2TP24B Datasheet(PDF) 67 Page - EM Microelectronic - MARIN SA |
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EM6812F2TP24B Datasheet(HTML) 67 Page - EM Microelectronic - MARIN SA |
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67 / 81 page  R EM6812 Copyright © 2005, EM Microelectronic-Marin SA 67 www.emmicroelectronic.com 14.2.1 Interrupt acquisition masking. At start up or after any reset all interrupt sources are masked (mask bits are ‘0’). To activate a specific interrupt source input the corresponding mask bit must be set ‘1’. Masking does not clear an existing interrupt but will prevent future interrupts on the same input. Refer to Figure 38, Interrupt acquisition architecture. 14.2.2 Interrupt acquisition Clearing A pending interrupt can be cleared in 3 ways 1. Reading the interrupt flag registers RegInt00, RegInt10 and RegInt20 will automatically clear all stored interrupts which were set prior to the read in the corresponding register. This read is normally done inside the interrupt subroutine to determine the source of the interrupt. 2. Each interrupt register bit can be individually cleared (set ‘0’) by writing ‘0’ to the corresponding RegInt00, RegInt10 and RegInt20 register bit. Write of ‘1’ has no effect. 3. At power up or after any reset all interrupt registers are reset. 14.2.3 Register map, Interrupt acquisition Table 58. Interrupt acquisition register overview Functions Register name Basic function RegInt00 Storage of incoming interrupts, priority 0 (highest) RegInt10 Storage of incoming interrupts, priority 1 Interrupt source inputs RegInt20 Storage of incoming interrupts, priority 2 (lowest) RegMsk00 Masking of incoming interrupts on priority 0 level RegMsk10 Masking of incoming interrupts on priority 1 level Interrupt masking RegMsk20 Masking of incoming interrupts on priority 2 level Table 59. Interrupt acquisition registers RegInt00 0x19 Bit Name Res Reset by R/W Description 7-0 Int0[7:0] 00 ResSys R*/W* Interrupt source flag register, priority 0 R*W*: auto-reset after read, only write of value ‘0’ is performed write of ‘1’ has no action RegInt10 0x18 Bit Name Res Reset by R/W Description 7-0 Int1[7:0] 00 ResSys R*/W* Interrupt source flag register, priority 1 R*W*: auto-reset after read, only write of value ‘0’ is performed write of ‘1’ has no action RegInt20 0x17 Bit Name Res Reset by R/W Description 7-0 Int2[7:0] 00 ResSys R*/W* Interrupt source flag register, priority 2 R*W*: auto-reset after read, only write of value ‘0’ is performed write of ‘1’ has no action RegMsk00 0x1C Bit Name Res Reset by R/W Description 7-0 Msk0[7:0] 00 ResSys R/W Interrupt mask register, priority 0 RegMsk10 0x1B Bit Name Res Reset by R/W Description 7-0 Msk1[7:0] 00 ResSys R/W Interrupt mask register, priority 1 RegMsk20 0x1A Bit Name Res Reset by R/W Description 7-0 Msk2[7:0] 00 ResSys R/W Interrupt mask register, priority 2 |
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