EM6812F2TP24B datasheet(48/81 Pages) EMMICRO

48 / 81 page

EM6812

www.emmicroelectronic.com

12.1.2 SPI terminal configuration

When the SPI is enabled EnSPI=’1’, the pads used in the port B for the transmission are automatically set in input or output

mode according to the configuration of the SPI. The pull resistors as well as the possible open-drain selections depend on

port B settings for the terminal direction.

Table 45. Terminal configurations

Pads

SPI pins

Direction

Pull-down

Pull-up

Open-drain

PB[7]

SIN

Input

Selectable

n.a.

PB[6]

SOUT

Output

Not selectable

Selectable in open-

drain mode

Selectable

PB[5]

SCLK

Output in master

mode.

Input in slave mode

Selectable in

slave mode

Selectable in slave or

open-drain master

mode

Selectable in

master mode

12.2

Functionality

12.2.1 Master and Slave modes

In slave mode SCLK is given externally and input on PB[5]. In master mode, SCLK is generated by the SPI and output on

PB[5].

Master/Slave selection as well as active clock selection in Master mode is done with the bits MS[2:0] in RegSPICfg.

Maximum Clock frequency in master mode is ½ of the internal high-speed clock (= 5MHz in case of RC 10MHz). Different

fix prescaler based clock frequencies and timer1 PWM frequencies are available as input clock.

MS[2:0] = 000 : Slave mode. SCLK = PB[5]

MS[2:0] = 001 : Master mode, SCLK = PWM1

(internal PWM signal coming for timer1)

MS[2:0] = 010 : Master mode, SCLK = PA[5]

(PA[5] input terminal)

MS[2:0] = 011 : Master mode, SCLK = Prc2CkSource

(clock source of prescaler2)

MS[2:0] = 100 : Master mode, SCLK = Pr2Ck[9]

(Output clock from prescaler2 bit[9])

MS[2:0] = 101 : Master mode, SCLK = Pr2Ck[8]

(Output clock from prescaler2 bit[8])

MS[2:0] = 110 : Master mode, SCLK = Pr1CkSource

(clock source of prescaler1)

MS[2:0] = 111 : Master mode, SCLK = Pr1Clk[14]

(Output clock from prescaler1 bit[14])

In master mode, SCLK is generated from the beginning until the end of the transmission. It is not necessary to enable and

disable the SPI for each burst. After each transmission, Start is automatically reset after 8 SPI clocks, except in cases

where the Load value is rewritten during the data transfer (AutoStart, fix data stream output).

12.2.2 Fix data stream Output (Auto-Start)

A new transmission will immediately follow the current transmission if the CPU writes in RegSPILoad while the Start = ‘1’.

Load_nShift is a flag indicating that the SPI is actually loading a value from RegSPILoad (Load_nShift = ‘1’) or if a

transmission is in progress (Load_nShift = ‘0’). The new RegSPILoad value must be loaded while LoadnShift is '0' (during

shift operation). A re-load after end of transmission, Start reads '0', will not trigger a new transmission. IrqSPI[1] can be

used to determine the reload time.

Note:

In Auto-Start mode, the SPI should run slower then the CPU especially when the CPU access RegSPIDat at the end

of the transmission.

12.2.3 SPI Interruptions

There are to interrupts generated by the SPI:

•

IrqSPI[1]: Generated at the beginning of the transmission on the first active edge of SCLK. It can be used in Auto-Start

mode to force the CPU to write the next value to transmit in RegSPILoad.

•

IrqSPI[0]: Generated at the end of the transmission on the last active edge of SCLK.

Both interruptions are maskable with RegMsk20[5:4]. They are on priority 2 in RegInt20[5:4].

EM6812F2TP24B Datasheet(PDF) 48 Page - EM Microelectronic - MARIN SA

EM6812F2TP24B Datasheet(HTML) 48 Page - EM Microelectronic - MARIN SA

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL