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EM6812F2TP24B Datasheet(PDF) 16 Page - EM Microelectronic - MARIN SA |
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EM6812F2TP24B Datasheet(HTML) 16 Page - EM Microelectronic - MARIN SA |
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16 / 81 page  R EM6812 Copyright © 2005, EM Microelectronic-Marin SA 16 www.emmicroelectronic.com 6 CPU Core, CR816L The µProcessor Core CR816L is a true low power RISC Core including a ‘one instruction cycle’ 8x8 hardware multiplier. Its main features are described below. 8 bits RISC register-memory processor based on a Harvard architecture 16 CPU internal registers (Accu, general purpose, Index, offset, status) 8b x 8b internal hardware multiplier 3 stage pipeline architecture (no delay slots or branch delays) 176 Kbytes max Program Memory size (64 Kinstruction, 22 bit wide) EM6812 uses max 22k Instruction 64 Kbytes max Data Memory size (organized in 256 x 256 kBytes pages) EM6812 uses max 608 Byte 8 max hardware subroutines and unlimited software subroutines EM6812 uses max 4 HW subroutines 5 different addressing modes direct addressing indexed addressing with immediate offset indexed addressing with register offset indexed addressing with post-incrementation of the offset indexed addressing with pre-decrementaion of the offset . Table 14: CR816L Instruction set Mnemonic ALU Instruction ADD ADDC AND yes yes yes Addition. Addition with carry. Logical AND. CALL CALLS CMP CMPA CMVD CMVS CPL1 CPL2 CPL2C no no yes yes yes yes yes yes yes Jump to subroutine. Jump to subroutine, using ip as return address. Unsigned compare. Signed compare. Conditional move, if carry clear. Conditional move, if carry set. One’s complementation. Two’s complementation. Two’s complementation with carry. DEC DECC yes yes Decrementation. Decrementation with carry. HALT no no Halt mode selection INC INCC yes yes Increment. Increment with carry. JCC no Conditional jump. MOVE MUL MULA yes yes yes Data move. Unsigned multiplication. Signed multiplication. NOP no No operation. OR yes Logical OR POP PUSH no no Pop ip index from hardware stack. Push ip index onto hardware stack. RET RETI no no Return from subroutine. Return from interrupt. SFLAG SHL SHLC SHR SHRA SHRC SUBD SUBDC SUBS SUBSC yes yes yes yes yes yes yes yes yes yes Save flags. Logical shift left. Logical shift left with carry. Logical shift right. Arithmetic shift right. Logical shift right with carry. Subtraction (op1 - op2). Subtraction with carry (op1 - op2). Subtraction (op2 - op1). Subtraction with carry (op2 - op1). TSTB yes Test bit. XOR yes Logical exclusive OR. Please refer to the CoolRISC 816L 8 bit Microprocessor Core Hardware and Software Manual Version 1.1 dated Mai 2002 |
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