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EM6812F2TP24B Datasheet(PDF) 49 Page - EM Microelectronic - MARIN SA |
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EM6812F2TP24B Datasheet(HTML) 49 Page - EM Microelectronic - MARIN SA |
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49 / 81 page  R EM6812 Copyright © 2005, EM Microelectronic-Marin SA 49 www.emmicroelectronic.com 12.2.4 SPI edge and synchronization selection Depending on the protocol, the SPI can shift the data’s on falling or rising edge of SCLK with bit PosnNegShft in register RegSPICfg. It is possible to resynchronize SOUT on the opposite edge shift clock with bit Synchro in register RegSPICfg: Figure 26 : Edge and synchronization selection 12.2.5 SPI start-up The SPI is enabled by bit EnSPI in RegCfgPB. Before enabling the SPI its configuration must be set. Configuration means, the clock selection, the edge selection and the synchronization of SOUT selection. If one of this parameter change while EnSPI = ‘1’, the transmitted data are not guaranteed. The last operation is to set Start to launch the transmission. • 1 st: Configuration settings : Clock, Edge, synch and MSB/LSB selection • 2 nd: Enabling the SPI: bit EnSPI in RegCfgPB • 3 rd: Write the load data in RegSPILoad • 4 th: Start the transmission with bit Start in RegSPICfg When the transmission is finished, RegSPIDat contains the received value coming through SIN. Note: This register is accessible in read mode only. It is possible to read it at any time but the data is not guaranteed during the transmission in slave mode and may not be the final value while Load_nShift = ‘0’. The value is guaranteed when Load_nShift = ‘1’. It is possible to use the interrupt IrqSPI[0] to start to read this register. The Start bit can be used to determine if a shift operation is ongoing or has finished. In Master mode the Start flag is synchronized with the next inversed active clock edge after writing the start bit. (The user writes the start bit but reads the start flag). In slave mode the start flag becomes active immediately after writing the start bit. After a full byte transfer the Start bit and also the start flag are reset. This may be used to determine end of transfer by software polling. 12.2.6 MSB or LSB first selection By default, MSBnLSB = ‘0’, the first transmission bit (receive or send) is the LSB. MSB first can be selected by writing MSBnLSB =’1’. The selection must be performed at the SPI setup, before loading or reading the transmission value. SCLK RegSPIDat XX AA 54 A9 52 A5 4B IrqSPI[0] SIN SOUT 010 101 0 10 010 110 1 55 1 96 IrqSPI[1] RegSPILoad 00 AA PosnNegShft = ‘1’ Synchro = ‘0’ Load_nShift SCLK RegSPIDat XX AA 54 A9 52 A5 4B IrqSPI[0] SIN SOUT 010 101 0 10 010 110 RegSPILoad 00 AA 1 55 1 96 IrqSPI[1] PosnNegShft = ‘0’ Synchro = ‘0’ Load_nShift SCLK RegSPIDat XX AA 54 A9 52 A5 4B IrqSPI[0] SIN SOUT 0 101 010 10 010 110 RegSPILoad 00 AA 55 1 96 IrqSPI[1] PosnNegShft = ‘1’ Synchro = ‘1’ Load_nShift SCLK RegSPIDat XX AA 54 A9 52 A5 4B IrqSPI[0] SIN SOUT 0 101 010 10 010 110 RegSPILoad 00 AA 1 55 1 96 IrqSPI[1] PosnNegShft = ‘0’ Synchro = ‘1’ Load_nShift |
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