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SH79F6488P/080PR Datasheet(PDF) 2 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR Datasheet(HTML) 2 Page - SINOWEALTH Electronic Ltd |
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2 / 152 page ![]() SH79F6488/SH79F6489 2 3. Block Diagram Pipelined 8051 architecture Reset circuit VDD Power Watch Dog Port 1 Configuration I/O P1.0 - P1.7 Port 0 Configuration I/O RESET EUART PGA JTAG ports (for debug) 64K Bytes Flash ROM Internal 256 Bytes External 2304 Bytes EEPROM 2048 Byte Internal Oscillator 12MHz RC External Interrupt P0.0 - P0.7 VDDR AGND OP 20-bit ADC 12-bit PWM0 12-bit PWM1 12-bit PWM2 XTAL1 XTAL2 Timer2 (16bit) Timer3 (16bit) Timer4(16bit) Base Timer GND Port 2 Configuration I/O P2.0 - P2.7 Port 3 Configuration I/O P3.0 - P3.7 Port 4 Configuration I/O P4.0 - P4.7 Port 5 Configuration I/O P5.0 - P5.7 Port 6 Configuration I/O P6.0 - P6.7 Port 7 Configuration I/O P7.0 - P7.7 Port 8 Configuration I/O P8.0 - P8.7 Regulator SPI LCD Driver 4 X 36, 5 X 35, 6 X 34 XTALX1 XTALX2 Oscillator 48MHz PLL USB (for SH79F6489) |
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