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SH79F6488P/080PR Datasheet(PDF) 64 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR Datasheet(HTML) 64 Page - SINOWEALTH Electronic Ltd |
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64 / 152 page  SH79F6488/SH79F6489 64 7.10 Interrupt 7.10.1 Features SH79F6488 : 14 interrupt sources SH79F6489 : 15 interrupt sources 4 interrupt priority levels The SH79F6488/SH79F6489 provides total 14 interrupt sources: 5 external interrupts (INT0/1/2/3/4; INT4 including INT40-47, which share the same vector address), 3 timer interrupts (Timer2, 3, 4), base timer interrupt, EUART interrupt, ADC Interrupt, PWM interrupts and SCM interrupt which share the same vector address. The SH79F6489 also provides USB Interrupt. 7.10.2 Interrupt Enable Control Each interrupt source can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains global interrupt enable bit, EA, which can enable/disable all the interrupts at once. Generally, after reset, all interrupt enable bits are set to 0, which means that all the interrupts are disabled. 7.10.3 Registers Table 7.43 Primary Interrupt Enable Register A8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN0 EA EADC ET2 ES ET3 EX1 ET4 EX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 EA All interrupt enable bit 0: Disable all interrupt 1: Enable all interrupt 6 EADC ADC interrupt enable bit 0: Disable ADC interrupt 1: Enable ADC interrupt 5 ET2 Timer2 overflow interrupt enable bit 0: Disable Timer2 overflow interrupt 1: Enable Timer2 overflow interrupt 4 ES EUART interrupt enable bit 0: Disable EUART interrupt 1: Enable EUART interrupt 3 ET3 Timer3 overflow interrupt enable bit 0: Disable Timer3 overflow interrupt 1: Enable Timer3 overflow interrupt 2 EX1 External interrupt1 enable bit 0: Disable external interrupt1 1: Enable external interrupt1 1 ET4 Timer4 overflow interrupt enable bit 0: Disable Timer4 overflow interrupt 1: Enable Timer4 overflow interrupt 0 EX0 External interrupt0 enable bit 0: Disable external interrupt0 1: Enable external interrupt0 |
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