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SH79F6488P/080PR Datasheet(PDF) 85 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR Datasheet(HTML) 85 Page - SINOWEALTH Electronic Ltd |
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85 / 152 page  SH79F6488/SH79F6489 85 8.3.6 Transmission Formats Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON, the clock polarity CPOL and the clock phase CPHA. CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted. The clock phase and polarity should be identical for the master and the communicating slave. SPEN (Internal) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) bit6 MSB bit5 bit4 bit3 bit2 bit1 LSB MISO (from Slave) bit6 MSB bit5 bit4 bit3 bit2 bit1 LSB SS (to Slave) SCK Cycle Number 1 2 3 4 5 6 7 8 Capture Point Data Transmission Format (CPHA = 0) If CPHA = 0, the first SCK edge is the capture strobe. Therefore the slave must begin driving its data before the first SCK edge, and a falling edge on the SS ——— pin is used to start the transmission. The SS ——— pin must be toggled high and then low between each byte transmitted. So SSDIS bit is invalid when CPHA = 0. SPEN (Internal) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) bit6 MSB bit5 bit4 bit3 bit2 bit1 LSB MISO (from Slave) SCK Cycle Number 1 2 3 4 5 6 7 8 Capture Point bit6 MSB bit5 bit4 bit3 bit2 bit1 LSB (to Slave) SS Data Transmission Format (CPHA = 1) If CPHA = 1, the master begins driving its MOSI pin on the first SCK edge. Therefore the slave uses the first SCK edge as a start transmission signal. So the user must put the SPDAT before the second edge of the first SCK. The SS ——— pin can remain low between transmissions. This format may be preferred in systems with only one master and only one slave. Byte1 Byte2 Byte3 MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) CPHA/SS ——— Timing Note: Before SPI is configured as Slave mode and CPOL bit in SPCON is cleared, the P2.4SCK pin must be set to input mode and enable pull-high resistor before SPEN bit in SPSTA is set to logic ‘1’. |
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