SH79F6488PSLASH080PR datasheet(86/152 Pages) SINOWEALTH

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SH79F6488/SH79F6489

8.3.7 Error Conditions

The following flags in the SPSTA signal SPI error conditions:

(1) Mode Fault (MODF)

Mode fault error in master mode SPI indicates that the level on the SS

———

pin is inconsistent with the actual mode of the device.

MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in

the following ways:



An SPI receiver/error CPU interrupt request is generated;



The SPEN bit in SPSTA is cleared. This disables the SPI;



The MSTR bit in SPCON is cleared.

When SS

———

Disable (SSDIS bit in the SPCON register) is cleared, the MODF flag is set when the SS

———

signal becomes ’0’.

However, as stated before, for a system with one Master, if the SS

———

pin of the master device is pulled low, there is no way that

another master attempts to drive the network. In this case, to prevent the MODF flag from being set, software can set the

SSDIS bit in the SPCON register and therefore making the SS

———

pin as a general-purpose I/O pin.

The user must clear the MODF bit by software, and enable SPEN in SPCON register again for further communication, and

enable MSTR bit to continue master mode.

(2) Write Collision (WCOL)

A write collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted. The WCOL bit is cleared by software.

(3) Overrun Condition (RXOV)

An overrun condition occurs when the master or slave tries to send several data bytes and the slave or master has not

cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receive shift register keep the byte that

SPIF was lastly set, also the SPI device will not receive any further data until SPIF was cleared. The SPIF still keep on

invoke interrupt before it is cleared, though the transmission can still be driven by SCK. RXOV does not generate an

interruption, the RXOV bit is cleared by software.

8.3.8 Interrupts

Two SPI status flags can generate a CPU interrupt requests SPIF & MODF.

Serial Peripheral data transfer flag: SPIF. This bit is set by hardware when a transfer has been completed.

Mode Fault flag: MODF. This bit becomes set to indicate that the level on the SS

———

pin is inconsistent with the mode of the SPI.

MODF with SSDIS reset will generate receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is

generated.

SPIF

MODF

SSDIS

SPI Receiver / Error

CPU Interrupt Request

SPI Transmitter

CPU Interrupt Request

SPI

CPU Interrupt Request

SPI Interrupt Requests Generation

SH79F6488P/080PR Datasheet(PDF) 86 Page - SINOWEALTH Electronic Ltd

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