SH79F6488PSLASH080PR datasheet(70/152 Pages) SINOWEALTH

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SH79F6488/SH79F6489

7.10.9 External Interrupt Inputs

The SH79F6488/SH79F6489 has 5 external interrupt inputs. External interrupt0-3 each has one vector address. External

interrupt 4 has 7 inputs; all of them share one vector address. These external interrupts can be programmed to be

level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in register TCON and register EXF1. If ITn = 0 (n = 0 - 1),

external interrupt 0/1 is triggered by a low level detected at the INT0/1 pin. If ITn = 1 (n = 0 - 1), external interrupt 0/1 is edge

triggered. In this mode if consecutive samples of the INT0/1 pin show a high level in one cycle and a low level in the next cycle,

interrupt request flag in register r EXF1 is set, causing an interrupt request. Since the external interrupt pins are sampled once

each machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper sampling.

If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine cycle,

and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request flag

is set. Notice that IE0-1 is automatically cleared by CPU when the service routine is called while IF4x should be cleared by

software. External interrupt4 operates in the similar ways except have different registers and have more selection of trigger.

If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is

generated, which will take 2 machine cycles. If the external interrupt is still asserted when the interrupt service routine is

completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEx (x = 0, 1, 2, 3) when the interrupt

is level sensitive, it simply tracks the input pin level.

If an external interrupt is enabled when the SH79F6488/SH79F6489 is put into Power down or Idle mode, the interrupt

occurrence will cause the processor to wake up and resume operation.

Note: IE0-3 is automatically cleared by CPU when the service routine is called while IF40-47 should be cleared by software.

1 Machine Cyle

>1 Machine Cycle

High-Level Threshold

Low-Level Threshold

>2 Machine Cycle

External Interrupt Detecting

7.10.10 Interrupt Summary

Source

Vector Address

Enable bits

Flag bits

Polling Priority

Interrupt No. (C51)

Reset

0000H

0 (higest)

INT0

0003H

EX0

IE0

Timer4

000BH

ET4

TF4

INT1

0013H

EX1

IE1

Timer3

001BH

ET3

TF3

EUART

0023H

RI+TI

Timer2

002BH

ET2

TF2+EXF2

ADC

0033H

EADC

ADCIF

SPI

003BH

ESPI

SPIF

INT2

0043H

EX2

IE2

INT3

004BH

EX3

IE3

INT4

0053H

EX4+IENC

IF45-40

USB (for 6489)

005BH

EUSB

Refers to the USB

12(6489)

PWM

0063H

EPWM+PWM0/1/2IE

PWM0/1/2IF

12(6488)/13(6489)

BaseTimer

006BH

EBT

BTIF

13(6488)/14(6489)

SCM

0073H

ESCM

SCMIF

14(6488)/15(6489)

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