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SH79F6488P/080PR Datasheet(PDF) 100 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR Datasheet(HTML) 100 Page - SINOWEALTH Electronic Ltd |
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100 / 152 page ![]() SH79F6488/SH79F6489 100 8.5.5 Error Detection Error detection is available when the SSTAT bit in register PCON is set to logic 1.The SSTAT bit must be logic 1 to access any of the status bits (FE, RXOV, and TXCOL). The SSTAT bit must be logic 0 to access the Mode Select bits (SM0, SM1, and SM2).All the 3 bits should be cleared by software after they are set, even when the following frames received without any error will not be cleared automatically. Transmit Collision The Transmit Collision bit (TXCOL bit in register SCON) reads ‘1’ if RI is set 0 and user software writes data to the SBUF register while a transmission is still in progress. If this occurs, the new data will be ignored and the transmit buffer will not be written. Receive Overrun The Receive Overrun bit (RXOV in register SCON) reads ‘1’ if a new data byte is latched into the receive buffer before software has read the previous byte. The previous data is lost when this happen. Frame Error The Frame Error bit (FE in register SCON) reads ‘1’ if an invalid (low) STOP bit is detected. Note: Before transmitting, TXD pin must be setted output high. 8.5.6 Registers Table 8.20 Power Control Register 87H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT - - GF1 GF0 PD IDL R/W R/W R/W - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - - 0 0 0 0 Bit Number Bit Mnemonic Description 7 SMOD Baud rate doubler 0: in Mode2, the baud-rate of EUART is 1/64 of the system clock 1: in Mode2, the baud-rate of EUART is 1/32 of the system clock 6 SSTAT SCON[7:5] function select bit 0: SCON[7:5] operates as SM0, SM1, SM2 1: SCON[7:5] operates as FE, RXOV, TXCOL 3-2 GF[1:0] General purpose flags for software use 1 PD Power-Down mode control bit 0 IDL Idle mode control bit |
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