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SH79F6488P/080PR Datasheet(PDF) 93 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR Datasheet(HTML) 93 Page - SINOWEALTH Electronic Ltd |
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93 / 152 page  SH79F6488/SH79F6489 93 8.5 EUART 8.5.1 Features The SH79F6488/SH79F6489 has one enhanced EUART with own baud rate generator The baud rate generator is an 15-bit up-counting timer Enhancements over the standard 8051 the EUART include Framing Error detection and automatic address recognition The EUART can be operated in four modes 8.5.2 EUART Mode Description The EUART can be operated in 4 modes. Users must initialize the SCON before any communication can take place. This involves selection of the Mode and the baud rate. In all of the 4 modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the incoming start bit if RI = 0 and REN = 1. The external transmitter will start the communication by transmitting the start bit. EUART Mode Summary SM0 SM1 Mode Type Baud Clock Frame Size Start Bit Stop Bit 9 th bit 0 0 0 Sych fSYS/(4 or 12) 8 bits NO NO None 0 1 1 Ansych own baud rate/16 10 bits 1 1 None 1 0 2 Ansych fSYS/(32 or 64) 11 bits 1 1 0, 1 1 1 3 Ansych own baud rate/16 11 bits 1 1 0, 1 Mode0: Synchronous Mode, Half duplex This mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on the RxD line. TxD is used to output the shift clock. The TxD clock is provided by the SH79F6488/SH79F6489 whether the device is transmitting or receiving. This mode is therefore a half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is transmitted/received first. The baud rate is programmable to either 1/12 or 1/4 of the system clock. This baud rate is determined in the SM2 bit (SCON.5). When this bit is set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock. The functional block diagram is shown below. Data enters and exits the serial port on the RxD line. The TxD line is used to output the SHIFT CLOCK. The SHIFT CLOCK is used to shift data into and out of the SH79F6488/SH79F6489. 12 4 SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI SHIFT CLOCK RX CLOCK LOAD SBUF RX START RX SHIFT Transmit Shift Register RXD Serial Port Interrupt TXD RI REN PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD SBUF Read SBUF Receive Shift Register Internal Data Bus Write to SBUF 1 0 SBUF ÷ ÷ System Clock SM2 |
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