SH79F6488PSLASH080PR datasheet(81/152 Pages) SINOWEALTH

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SH79F6488/SH79F6489

8.3 Serial Peripheral Interface (SPI)

8.3.1 Features

 Full-duplex, three-wire synchronous transfers

 Master or slave operation

 Six programmable master clock rates

 Serial clock with programmable polarity and phase

 Master mode fault error flag with MCU interrupt capability

 Write collision flag protection

 Selectable LSB or MSB transfer

The Serial Peripheral Interface (SPI) Module allows full-duplex, synchronous, serial communication between the MCU and

peripheral devices, including other MCUs.

The following diagram shows a typical SPI bus configuration using one master controller and many slave peripherals. The bus

is made of three wires connecting all the devices. The master device selects the individual slave devices by using four pins of a

parallel port to control the four SS pins of the Slave devices.

MISO

MOSI

SCK

Master

Port0.0

Port0.1

Port0.2

Port0.3

Slave

8.3.2 Signal Description

(1) Master Output Slave Input (MOSI)

This 1-bit signal is directly connected between the master device and slave devices. The MOSI line is used to transfer data in

series from the master to the slave. Therefore, it is an output signal from the master, and an input signal to a slave.

(2) Master Input Slave Output (MISO)

This 1-bit signal is directly connected between the slave devices and master device. The MISO line is used to transfer data in

series from the slave to the master. Therefore, it is an output signal from the slave, and an input signal to the master. The MISO

pin is placed in a high-impedance state when the SPI operates as a slave that is not selected (SS

———

high).

A static high level on the SS

———

pin puts the MISO line of a slave in a high-impedance state.

(3) SPI Serial Clock (SCK)

This signal is used to synchronize the data movement both in and out of the devices through their MOSI and MISO lines. It

is driven by the master for eight clock cycles, which allows exchanging one byte on the serial lines. The SCK signal is

ignored by a SPI slave when the slave is not selected (SS

———

high).

(4) Slave Select (SS

———

)

Each slave peripheral is selected by one slave select pin (SS

———

). This signal must stay low for any active slave. It is obvious

that only one master (SS

———

high) can drive the network. The master may select each slave device by software through port

pins. To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the master for a transmission.

In a master configuration, the SS

———

line can be used in conjunction with the MODF flag in the SPI status register to prevent

multiple masters from driving MOSI and SCK.

The SS

———

pin could be used as a general IO if the following conditions are met:

(a) The device is configured as a master and the SSDIS control bit in SPCON is set. This kind of configuration can happen

when only one master is driving the network. Therefore, the MODF flag in the SPSTA will never be set.

(b) The device is configured as a slave with CPHA and SSDIS control bits set. This kind of configuration can happen when

the network comprises only one master and one slave only. Therefore, the device should always be selected and the

master will never use the slave’s SS

———

pin to select the target communication slave.

Note: When CPHA = ‘0’, a falling edge of SS

———

pin is used to start the transmission.

SH79F6488P/080PR Datasheet(PDF) 81 Page - SINOWEALTH Electronic Ltd

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