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SH79F6488P/080PR Datasheet(PDF) 88 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR Datasheet(HTML) 88 Page - SINOWEALTH Electronic Ltd |
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88 / 152 page  SH79F6488/SH79F6489 88 Table 8.11 Serial Peripheral Status Register A5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPSTA SPEN SPIF MODF WCOL RXOV - - - R/W R/W R/W R/W R/W R/W - - - Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 - - - Bit Number Bit Mnemonic Description 7 SPEN SPI Enable 0: Disable the SPI interface 1: Enable the SPI interface 6 SPIF Serial Peripheral data transfer flag 0: Clear by software 1: Set by hardware to indicate that the data transfer has been completed 5 MODF Mode Fault 0: Cleared by software 1: Set by hardware to indicate that the SS ——— pin is at inappropriate logic level 4 WCOL Write Collision flag 0: Cleared by software to indicate write collision has bee processed 1: Set by hardware to indicate that a collision has been detected 3 RXOV Receive Overrun 0: Cleared by software to indicate receive overrun has bee processed 1: Set by hardware to indicate that a receive overrun has been detected Table 8.12 Serial Peripheral Data Register A6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPDAT SPDAT7 SPDAT6 SPDAT5 SPDAT4 SPDAT3 SPDAT2 SPDAT1 SPDAT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SPDAT[7:0] A write to SPDAT places data directly into the transfer shift register. A Read of the SPDAT returns the value located in the receive shift register. Note: When SPI is disabled, the data of SPDAT is invalid. |
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