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SH79F6488P/080PR Datasheet(PDF) 24 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR Datasheet(HTML) 24 Page - SINOWEALTH Electronic Ltd |
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24 / 152 page  SH79F6488/SH79F6489 24 7.1.2 Enhanced CPU core SFRs Extended 'MUL' and 'DIV' instructions: 16bits*8bits, 16bits/8bits Dual Data Pointer Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH79F6488/SH79F6489 has modified 'MUL' and 'DIV' instructions. These instructions support 16 bits operand. A new register - the register is applied to hold the upper part of the operand/result. The AUXC register is used during 16 bits operand multiply and divide operations. For other instructions it can be treated as another scratch pad register. After reset, the CPU is in standard mode, which means that the 'MUL' and 'DIV' instructions are operating like the standard 8051 instructions. To enable the 16 bits mode operation, the corresponding enable bit in the INSCON register must be set. Operation Result A B AUXC MUL INSCON.2 = 0; 8-bit mode (A)*(B) Low Byte High Byte --- INSCON.2 = 1; 16-bit mode (AUXC A)*(B) Low Byte Middle Byte High Byte DIV INSCON.3 = 0; 8-bit mode (A)/(B) Quotient Low Byte Remainder --- INSCON.3 = 1; 16-bit mode (AUXC A)/(B) Quotient Low Byte Remainder Quotient High Byte Dual Data Pointer Using two data pointers can accelerate data memory moves. The standard data pointer is called DPTR and the new data pointer is called DPTR1. DPTR1 is the same with DPTR, which consists of a high byte (DPH1) and a low byte (DPL1). Its intended function is to hold a 16-bit address, but it may be manipulated as a 16-bit register or as two independent 8-bit registers. The DPS bit in INSTCON register is used to choose the active pointer. The user can switch data pointers by toggling the DPS bit. And all DPTR-related instructions will use the currently selected data pointer. 7.1.3 Registers Table 7.2 Data Pointer Select Register 86H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INSCON BKS1 BKS0 - - DIV MUL - DPS R/W R/W R/W - - R/W R/W - R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - - 0 0 - 0 Bit Number Bit Mnemonic Description 7-6 BKS[1:0] SFR Bank Selection Bit 00: SFR Bank0 selected 01: SFR Bank1 selected 1x: reserved 3 DIV 16-bit/8-bit Divide Selection Bit 0: 8-bit Divide 1: 16-bit Divide 2 MUL 16-bit/8-bit Multiply Selection Bit 0: 8-bit Multiply 1: 16-bit Multiply 0 DPS Data Pointer Selection Bit 0: Data pointer 1: Data pointer1 |
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