SH79F6488PSLASH080PR datasheet(83/152 Pages) SINOWEALTH

83 / 152 page

SH79F6488/SH79F6489

8.3.5 Operating Modes

The Serial Peripheral Interface can be configured as one of the two modes, master mode or slave mode. The configuration and

initialization of the SPI module is made through SPCON (the serial peripheral control register) and SPSTA (the serial peripheral

status register). Once the SPI is configured, the data exchange is made using SPCON, SPSTA and SPDAT (the serial

peripheral data register).

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial

clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A slave select line (SS

———

)

allows individual selection of a SPI slave; SPI slaves that are not selected do not interfere with SPI bus activities.

When the SPI master transmits data to the SPI slave via the MOSI line, the SPI slave responds by sending data to the SPI

master via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock.

Both transmit shift register and receive shift register uses the same SFR Address, a write operation to SPDAT will write to the

transmit shift register, and a read operation from SPDAT will retrieve the data in receive shift register.

Master MCU

8-bit Shift Register

SPI

Clock Generator

MISO

MOSI

SCK

VDD

MISO

MOSI

SCK

VSS

Slave MCU

8-bit Shift Register

Full-Duplex Master-Slave Interconnection Diagram

Master Mode

(1) Enable

A SPI master device initiates all data transfers on a SPI bus. The SPI operates in master mode when the MSTR is set in

SPCON register. Only one master can initiate transmission.

(2) Transmit

When in SPI master mode, writing a byte of data to the SPI data register (SPDAT) will write to the transmit shift buffer. If the

transmit shift register already contains data, the SPI master will generate a WCOL signal to indicate writing too fast. But the

data in transmit shift register will not be affected, and the transmission continues uninterrupted. Else if the transmit shift

register is empty, the SPI master will immediately shifts out the data serially on the MOSI line while providing the serial clock

on SCK. The SPIF flag in SPSTA register is set to logic ‘1’ at the end of the transfer. If interrupts are enabled, an interrupt

request is generated when the SPIF flag is set.

(3) Receive

While the master transfers data to a slave on the MOSI line, the addressed slave simultaneously transfers the contents of its

transmit shift register to the master’s receive shift register on the MISO line in a full-duplex operation. Therefore, the SPIF

flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred

MSB-first or LSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive

buffer where it can be read by the processor by reading SPDAT. If an overrun occurs, RXOV signal will be set to indicate

data over-run occurs, and the receive shift register keep the byte that SPIF was lastly set, also the SPI master will not

receive any further data until SPIF was cleared.

SH79F6488P/080PR Datasheet(PDF) 83 Page - SINOWEALTH Electronic Ltd

SH79F6488P/080PR Datasheet(HTML) 83 Page - SINOWEALTH Electronic Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL