SH79F6488PSLASH080PR datasheet(99/152 Pages) SINOWEALTH

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SH79F6488/SH79F6489

8.5.4 Multi-Processor Communication

Software Address Recognition

Modes 2 and 3 of the EUART have a special provision for multi-processor communication. In these modes, 9 data bits are

received. The 9th bit goes into RB8. Then a stop bit follows. The EUART can be programmed such that when the stop bit is

received, the EUART interrupt will be activated (i.e. the request flag RI is set) only if RB8 = 1. This feature is enabled by setting

the bit SM2 in SCON.

A way to use this feature in multiprocessor communications is as follows. lf the master processor wants to transmit a block of

data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from

a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte.

With SM2 = 1, no other slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each

slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to

receive the data bytes that will be coming. After having received a complete message, the slave sets SM2 again. The slaves

that were not addressed leave their SM2 set and go on with their business, ignoring the incoming data bytes.

Note: In Mode0, SM2 is used to select baud rate doubling. In Mode1, SM2 can be used to check the validity of the stop bit. If

SM2 = 1 in Mode1, the receive interrupt will not be activated unless a valid stop bit is received.

Automatic (Hardware) Address Recognition

In Mode2 & 3, setting the SM2 bit will configure EUART act as following: when a stop bit is received, EUART will generate an

interrupt only if the 9

th bit that goes into RB8 is logic 1 (address byte) and the received data byte matches the EUART slave

address. Following the received address interrupt, the slave should clear its SM2 bit to enable interrupts on the reception of the

following data byte(s).

The 9-bit mode requires that the 9

th information bit is a 1 to indicate that the received information is an address and not data.

When the master processor wants to transmit a block of data to one of the slaves, it first sends out the address of the targeted

slave (or slaves). All the slave processors should have their SM2 bit set high when waiting for an address byte, which ensures

that they will be interrupted only by the reception of an address byte. The Automatic address recognition feature further ensures

that only the addressed slave will be interrupted. The address comparison is done by hardware not software.

After being interrupted, the addressed slave clears the SM2 bit to receive data bytes. The un-addressed slaves will be

unaffected, as they will be still waiting for their address. Once the entire message is received, the addressed slave should set its

SM2 bit to ignore all transmissions until it receives the next address byte.

The Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking

the Given Address. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are

used to define the slave’s address, SADDR, and the address mask, SADEN. The slave address is an 8-bit value specified in the

SADDR register. The SADEN register is actually a mask for the byte value in SADDR. If a bit position in SADEN is 0, then the

corresponding bit position in SADDR is don’t care. Only those bit positions in SADDR whose corresponding bits in SADEN are

1 are used to obtain the Given Address. This gives the user flexibility to address multiple slaves without changing the slave

address in SADDR. Use of the Given Address allows multiple slaves to be recognized while excluding others.

Slave 1

Slave 2

SADDR

10100100

10100111

SADEN (0 mask)

11111010

11111001

Given Address

10100x0x

10100xx1

Broadcast Address (OR)

1111111x

11111111

The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don’t care, while for slave 2 it is 1. Thus to communicate

only with slave 1, the master must send an address with LSB = 0 (10100000). Similarly the bit 1 is 0 for slave 1 and don’t care

for slave 2. Hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the

master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The bit 2

position is don’t care for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101).

The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the

logical OR of the SADDR and SADEN. The zeros in the result are defined as don’t cares. In most cases, the Broadcast Address

is FFh, this address will be acknowledged by all slaves.

On reset, the SADDR and SADEN are initialized to 00h. This results in Given Address and Broadcast Address being set as

XXXXXXXX (all bits don’t care). This effectively removes the multiprocessor communications feature, since any selectivity is

disabled. This ensures that the EUART 0 will reply to any address, which it is backwards compatible with the 80C51

microcontrollers that do not support automatic address recognition. So the user may implement multiprocessor by software

address recognition mentioned above.

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