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SH79F6488P/080PR Datasheet(PDF) 104 Page - SINOWEALTH Electronic Ltd |
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SH79F6488P/080PR Datasheet(HTML) 104 Page - SINOWEALTH Electronic Ltd |
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104 / 152 page  SH79F6488/SH79F6489 104 8.6.3 Registers Table 8.26 ADC Control Register 93H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON ADON ADCIF VREFIN VREFS SCH3 SCH2 SCH1 SCH0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 ADON ADC Control bit 0: Disable ADC module 1: Enable ADC module, set to start AD convert 6 ADCIF ADC Interrupt Flag bit 0: No ADC interrupt generate, must be cleared by software 1: Set by hardware, one conversion complete 5 VREFIN Internal Reference voltage select bit 0: Select VREF1, the value is controlled by VREF[1:0], divided by VDDR, same source of VDDR 1: Select VREF2, the voltage is 1.19V,not the same source of VDDR. 4 VREFS ADC Reference voltage select bit 0: Select internal reference voltage, VREFOS bit must write “1” 1: Select external reference voltage in VREF pin, VREFOS bit must write “1” 3-0 SCH[3:0] ADC Channel Select bits 0000: ADC differential input AIN0+, AIN0- 0001: ADC differential input AIN1+, AIN1- 0010: ADC differential input AIN2+, AIN2- 0011: PGA internal short, connect with VCOM 0100: ADC input AN0 0101: ADC input AN1 0110: ADC input AN2 0111: ADC input AN3 1000: reserved 1001: PGA Positive connect with VREF, PGA Negative connect with AGND 1010: PGA Positive connect with AGND, PGA Negative connect with VREF Others: ADC differential input AIN0+, AIN0- Notes: (1) Clearing ADON bit during converting time will stop current AD conversion. (2) AN0/1/2/3 inputs are Isolated by OP, connect to PGA through divider resistors, keep input voltage < VDDR-0.3V. (3) VREF pin needs to be connect 104 capacitance between AGND. (4) AN0/1/2/3 Single-ended input. PGA gain can't be more than eight times.make sure PGA input voltage *gain < VREF. |
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