SH79F6488PSLASH080PR datasheet(105/152 Pages) SINOWEALTH

105 / 152 page

SH79F6488/SH79F6489

105

ADC Channel Diagram:

PGA

ADC

module

AINx-

AINx+

SCH [3:0] = 0000

GAIN [3:0]

ADC

module

SCH [3:0] = 0011

GAIN [3:0]

VREF

VCOM

SCH [3:0] = 0010

SCH [3:0] = 0001

x = 0 - 2

SCH [3:0] = 0101

SCH [3:0] = 0110

SCH [3:0] = 0100

100K

50K

150K

AGND

AN0/1/2/3

PGA

ADC

module

GAIN [3:0]

VREF

SCH [3:0] = 0111

Note:

(1) If SCH[3:0] = 0100, 0101, 0110 or0111 it used to measure voltage value of VDD. AN0/1/2/3 inputs are Isolated by OP,

connect to PGA through divider resistors, ADC will sample 1/6 voltage of the sigle-ended inputs. keep input voltage <

VDDR-0.3V.

(2) VCOM = 0.5VDDR

Table 8.27 ADC Clock Register

94H

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ADT

TADC7

TADC6

TADC5

TADC4

TADC3

TADC2

TADC1

TADC0

R/W

Reset Value

(POR/WDT/LVR/PIN)

Bit Number

Bit Mnemonic

Description

7-0

TADC[7:0]

ADC Clock Register

ADC Clock = fSYS/2/(256-TADC[7:0])

Note:

(1) The fSYS is system Clock, it will affect ADC clock when system clock prescaler is changed;

(2) ADT register sets ADC working clock, 100kHz is recommended as ADC clock;

(3) The relation between ADC clock and ADT: ADC clock = fSYS/2/(256-TADC[7:0]);

(4) ADC conversion rate: ADC clock/4000;

(5) AC power 50Hz noise will be filtered out when ADC conversion rate is 25Hz;

(6) AC power 60Hz noise will be filtered out when ADC conversion rate is 20Hz;

(7) Both AC power 50Hz and 60Hz noise will be filtered out when ADC conversion rate is 10Hz;

(8) ADC precision will affect when conversion rate more than 50Hz.(Refer to electrical characteristics section for details).

SH79F6488P/080PR Datasheet(PDF) 105 Page - SINOWEALTH Electronic Ltd

SH79F6488P/080PR Datasheet(HTML) 105 Page - SINOWEALTH Electronic Ltd

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