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HC705P6AGRS/D Datasheet(PDF) 37 Page - NXP Semiconductors |
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HC705P6AGRS/D Datasheet(HTML) 37 Page - NXP Semiconductors |
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37 / 134 page  General Release Specification COP Watchdog Timer Considerations MC68HC705P6A — Rev. 1.0 General Release Specification Operating Modes 3.6 COP Watchdog Timer Considerations The COP watchdog timer is active in user mode of operation when the COP bit in the MOR is set. Executing the STOP instruction when the SWAIT bit in the MOR is clear will cause the COP to be disabled. Therefore, it is recommended that the STOP instruction be modified to produce halt mode (set bit SWAIT in the MOR) if the COP watchdog timer is required to function at all times. Furthermore, it is recommended that the COP watchdog timer be disabled for applications that will use the wait mode for time periods that will exceed the COP timeout period. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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