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HC705P6AGRS/D Datasheet(PDF) 41 Page - NXP Semiconductors |
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HC705P6AGRS/D Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 134 page ![]() General Release Specification Internal Resets MC68HC705P6A — Rev. 1.0 General Release Specification Resets voltage range (between VSS–VDD), the COP watchdog timer’s output will be restored if the COP bit in the MOR is set. The COP register is shared with the LSB of an unused vector address as shown in Figure 4-2. Reading this location will return the programmed value of the unused user interrupt vector, usually zero. Writing to this location will clear the COP watchdog timer. When the COP watchdog timer expires, it will generate the RST signal and reset the MCU. If any other reset function is active at the end of the COP reset signal, the RST signal will remain in the reset condition until the other reset condition(s) end. When the reset condition ends, the MCU’s operating mode will be selected (see Table 3-1). $1FF0 Bit 7 654321 Bit 0 Read: 00000000 Write: COPR = Unimplemented Figure 4-2. Unused Vector and COP Watchdog Timer Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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