HC705P6AGRSSLASHD datasheet(51/134 Pages) NXP

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General Release Specification

Port B

MC68HC705P6A — Rev. 1.0

General Release Specification

Input/Output Ports

6.4 Port B

Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with

the SIOP communications subsystem. The port B data register is located

at address $0001 and its data direction register (DDR) is located at

address $0005. The contents of the port B data register are

indeterminate at initial powerup and must be initialized by user software.

Reset does not affect the data registers, but clears the DDRs, thereby

setting all of the port pins to input mode. Writing a one to a DDR bit sets

the corresponding port pin to output mode (see Figure 6-2).

Port B may be used for general I/O applications when the SIOP

subsystem is disabled. The SPE bit in register SPCR is used to

enable/disable the SIOP subsystem. When the SIOP subsystem is

enabled, port B registers are still accessible to software. Writing to either

of the port B registers while a data transfer is under way could corrupt

the data. See Section 7. Serial Input/Output Port for a discussion of

the SIOP subsystem.

Figure 6-2. Port B I/O Circuitry

READ $0001

WRITE $0001

READ $0005

DATA

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0005

DATA DIRECTION

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D Datasheet(PDF) 51 Page - NXP Semiconductors