HC705P6AGRSSLASHD datasheet(69/134 Pages) NXP

69 / 134 page

General Release Specification

Timer I/O Registers

MC68HC705P6A — Rev. 1.0

General Release Specification

Capture/Compare Timer

OCIE — Output Compare Interrupt Enable

This read/write bit enables interrupts caused by an active signal on

the TCMP pin. Resets clear the OCIE bit.

1 = Output compare interrupts enabled

0 = Output compare interrupts disabled

TOIE — Timer Overflow Interrupt Enable

This read/write bit enables interrupts caused by a timer overflow.

Reset clear the TOIE bit.

1 = Timer overflow interrupts enabled

0 = Timer overflow interrupts disabled

IEDG — Input Edge

The state of this read/write bit determines whether a positive or

negative transition on the TCAP pin triggers a transfer of the contents

of the timer register to the input capture register. Resets have no

effect on the IEDG bit.

1 = Positive edge (low to high transition) triggers input capture

0 = Negative edge (high to low transition) triggers input capture

OLVL — Output Level

The state of this read/write bit determines whether a logic one or logic

zero appears on the TCMP pin when a successful output compare

occurs. Resets clear the OLVL bit.

1 = TCMP goes high on output compare

0 = TCMP goes low on output compare

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705P6AGRS/D Datasheet(PDF) 69 Page - NXP Semiconductors