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HC705P6AGRS/D Datasheet(PDF) 71 Page - NXP Semiconductors |
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HC705P6AGRS/D Datasheet(HTML) 71 Page - NXP Semiconductors |
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71 / 134 page  General Release Specification Timer I/O Registers MC68HC705P6A — Rev. 1.0 General Release Specification Capture/Compare Timer 8.4.3 Timer Registers (TRH and TRL) The timer registers, shown in Figure 8-4, contains the current high and low bytes of the 16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer registers has no effect. Figure 8-4. Timer Registers (TRH and TRL) TRH $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 Write Reset: 11111111 TRL $0019 Bit 7 6 5 4 3 2 1 Bit 0 Read: BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Write: Reset: 11111100 = Unimplemented Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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