AVR32AP datasheet(65/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

5.2.2

Predictable instructions

The following instructions are predictable, and may be placed in the BTB.

5.2.3

Foldable instructions

All instructions can be folded into a branch instruction, except for instructions that are predicted

by the BTB. These instructions are listed in Table 5-1. In other words, br {k8, k21} and rjmp {k10,

k21} can not be folded together with any of the instructions listed in Table 5-1. The three call

instructions listed in the table can not fold into any other instructions.

All Java branches can be predicted and can be merged as described in the Java Technical

Reference.

5.2.4

Branch target buffer

The branch target buffer (BTB) is a n-entry direct mapped cache. The indexing function used is

index = fetchadr[n+2:2]. This function is expected to present a good hashing function into the

cache, distributing competing entries evenly into the cache. Note that bits [n+2:2] in the instruc-

tion address is used for BTB lookup. This will map two sequential compact branches to the same

BTB entry. This should not reduce performance, as the case where two sequential branches

both are predicted taken is meaningless. The other bits in the instruction address is used as

cache tag fields.

Each line in the BTB cache cache has the following format. The Ext field indicates if the branch

instruction is an extended instruction.

Figure 5-2.

BTB entry.

The history bits are implemented as a 2-bit saturating counter. When a new branch is detected,

the counter is initialized to Strong Taken. The FSM has the following coding and transitions:

Table 5-1.

Predictable instructions

Instruction

Conditiona

lMode

Can fold other

instructions

Can merge with other

instructions

br k8

Yes

RISC

Yes

br k21

Yes

RISC

Yes

rjmp k10

RISC

Yes

rjmp k21

RISC

Yes

rcall k10

RISC

rcall k21

RISC

if{cond}

Yes

Java

Yes

ifcmp{cond}

Yes

Java

Yes

Branch Address

Target address

History[1:0]

Tag

Data

Valid

Ext

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